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Commit 91d181dd authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
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drm/i915: vlv: handle only enabled pipestat interrupt events 



Atm we call the handlers for pending pipestat interrupt events even if
they aren't explicitly enabled by i915_enable_pipestat(). This isn't an
issue for events other than the vblank start event, since those are
always enabled anyways. Otoh, we enable the vblank start event
on-demand, so we'll end up calling the vblank handler at times when they
are disabled.

I haven't checked if this causes any real problem, but for consistency
and to remove some overhead we should still fix this by clearing /
handling only the enabled interrupt events. Also this is a dependency
for the upcoming VLV power domain patchset where we need to disable all
the pipestat interrupts whenever the display power well is off.

v2:
- inline the status->enable mask mapping (Ville)
- don't check for invalid PSR bit on platforms other than VLV (Ville)

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Frob conflict due to different merge order.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 10c59c51

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1436,6 +1436,7 @@ typedef struct drm_i915_private { 
	};

	u32 gt_irq_mask;

	u32 pm_irq_mask;

	u32 pipestat_irq_mask[I915_MAX_PIPES];



	struct work_struct hotplug_work;

	bool enable_hotplug_processing;

drivers/gpu/drm/i915/i915_irq.c

+32 −3
Original line number Diff line number Diff line
@@ -419,6 +419,16 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 
	return ret;

}



static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,

						  enum pipe pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);



	return !intel_crtc->cpu_fifo_underrun_disabled;

}



/**

 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages

 * @dev: drm device
@@ -488,6 +498,8 @@ __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 
	if ((pipestat & enable_mask) == enable_mask)

		return;



	dev_priv->pipestat_irq_mask[pipe] |= status_mask;



	/* Enable the interrupt, clear any pending status */

	pipestat |= enable_mask | status_mask;

	I915_WRITE(reg, pipestat);
@@ -510,6 +522,8 @@ __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 
	if ((pipestat & enable_mask) == 0)

		return;



	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;



	pipestat &= ~enable_mask;

	I915_WRITE(reg, pipestat);

	POSTING_READ(reg);
@@ -1540,18 +1554,33 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) 
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 pipe_stats[I915_MAX_PIPES];

	u32 pipe_stats[I915_MAX_PIPES] = { };

	int pipe;



	spin_lock(&dev_priv->irq_lock);

	for_each_pipe(pipe) {

		int reg = PIPESTAT(pipe);

		int reg;

		u32 mask;



		if (!dev_priv->pipestat_irq_mask[pipe] &&

		    !__cpu_fifo_underrun_reporting_enabled(dev, pipe))

			continue;



		reg = PIPESTAT(pipe);

		pipe_stats[pipe] = I915_READ(reg);



		/*

		 * Clear the PIPE*STAT regs before the IIR

		 */

		if (pipe_stats[pipe] & 0x8000ffff)

		mask = PIPESTAT_INT_ENABLE_MASK;

		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))

			mask |= PIPE_FIFO_UNDERRUN_STATUS;

		if (iir & I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe))

			mask |= dev_priv->pipestat_irq_mask[pipe];

		pipe_stats[pipe] &= mask;



		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |

					PIPESTAT_INT_STATUS_MASK))

			I915_WRITE(reg, pipe_stats[pipe]);

	}

	spin_unlock(&dev_priv->irq_lock);

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -997,6 +997,10 @@ 
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)

#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)

#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)

#define I915_DISPLAY_PIPE_EVENT_INTERRUPT(pipe)				\

	((pipe) == PIPE_A ? I915_DISPLAY_PIPE_A_EVENT_INTERRUPT :	\

	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)



#define I915_DEBUG_INTERRUPT				(1<<2)

#define I915_USER_INTERRUPT				(1<<1)

#define I915_ASLE_INTERRUPT				(1<<0)