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Commit 918f618f authored by huangdaode's avatar huangdaode Committed by David S. Miller
Browse files

net: hns: bug fix about hisilicon TSO BD mode 



The current upstreaming code fails to set the tso_mode register
when initilizes, when processes large size packets, the default 4 bd is
not enough, so this patch initilizes it and set the default value to 8 bds

Signed-off-by: default avatarDaode Huang <huangdaode@hisilicon.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 23195ec0

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

+11 −2
Original line number Diff line number Diff line
@@ -369,8 +369,17 @@ int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common) 
	dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,

		       HNS_RCB_COMMON_ENDIAN);



	if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {

		dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0);

		dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1);

	} else {

		dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,

				 RCB_COM_CFG_FNA_B, false);

		dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,

				 RCB_COM_CFG_FA_B, true);

		dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG,

				 RCB_COM_TSO_MODE_B, HNS_TSO_MODE_8BD_32K);

	}



	return 0;

}

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h

+3 −0
Original line number Diff line number Diff line
@@ -54,6 +54,9 @@ struct rcb_common_cb; 
#define HNS_DUMP_REG_NUM			500

#define HNS_STATIC_REG_NUM			12



#define HNS_TSO_MODE_8BD_32K			1

#define HNS_TSO_MDOE_4BD_16K			0



enum rcb_int_flag {

	RCB_INT_FLAG_TX = 0x1,

	RCB_INT_FLAG_RX = (0x1 << 1),

drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -363,6 +363,8 @@ 
#define RCB_COM_CFG_FA_REG			0x3C

#define RCB_COM_CFG_PKT_TC_BP_REG		0x40

#define RCB_COM_CFG_PPE_TNL_CLKEN_REG		0x44

#define RCBV2_COM_CFG_USER_REG			0x30

#define RCBV2_COM_CFG_TSO_MODE_REG		0x50



#define RCB_COM_INTMSK_TX_PKT_REG		0x3A0

#define RCB_COM_RINT_TX_PKT_REG			0x3A8
@@ -860,6 +862,9 @@ 


#define PPE_COMMON_CNT_CLR_CE_B	0

#define PPE_COMMON_CNT_CLR_SNAP_EN_B	1

#define RCB_COM_TSO_MODE_B	0

#define RCB_COM_CFG_FNA_B	1

#define RCB_COM_CFG_FA_B	0



#define GMAC_DUPLEX_TYPE_B 0