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Commit 9139227d authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Mike Turquette
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clk: tegra114: correctly output clk_32k 



Tegra has a blink timer register that allows to modulate the
clk_32k clock before outputting it. Since clk_32k is presented to the
kernel as a fixed clock, make sure this register does not tamper with
the clock frequency and that clk_32k is outputted as-is, similarly to
what is done on t20 and t30.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 995968e4

drivers/clk/tegra/clk-tegra114.c

+3 −0
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ 
#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20

#define PMC_CTRL 0

#define PMC_CTRL_BLINK_ENB 7

#define PMC_BLINK_TIMER 0x40



#define OSC_CTRL			0x50

#define OSC_CTRL_OSC_FREQ_SHIFT		28
@@ -1625,6 +1626,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 
	clks[clk_out_3] = clk;



	/* blink */

	/* clear the blink timer register to directly output clk_32k */

	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);

	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,

				pmc_base + PMC_DPD_PADS_ORIDE,

				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);