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Commit 911d49c7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.9-tag2' of... 

Merge tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull renesas r8a7796 SDHI clock support from Geert Uytterhoeven:

Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W
(r8a7796) SoC.

* tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add SDIF clocks
  clk: renesas: r8a7796: Add GPIO clocks
parents 61f800de 07496981

drivers/clk/renesas/r8a7796-cpg-mssr.c

+18 −0
Original line number Original line Diff line number Diff line
@@ -70,6 +70,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),

	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),

	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),





	/* Core Clock Outputs */

	/* Core Clock Outputs */

	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
@@ -93,6 +94,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),

	DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),

	DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),

	DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),





	DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,    0x0074),

	DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,    0x0078),

	DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,    0x0268),

	DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,    0x026c),



	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
@@ -104,8 +110,20 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 




static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {

static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {

	DEF_MOD("scif2",		 310,	R8A7796_CLK_S3D4),

	DEF_MOD("scif2",		 310,	R8A7796_CLK_S3D4),

	DEF_MOD("sdif3",		 311,	R8A7796_CLK_SD3),

	DEF_MOD("sdif2",		 312,	R8A7796_CLK_SD2),

	DEF_MOD("sdif1",		 313,	R8A7796_CLK_SD1),

	DEF_MOD("sdif0",		 314,	R8A7796_CLK_SD0),

	DEF_MOD("rwdt0",		 402,	R8A7796_CLK_R),

	DEF_MOD("rwdt0",		 402,	R8A7796_CLK_R),

	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),

	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),

	DEF_MOD("gpio7",		 905,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio6",		 906,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio5",		 907,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio4",		 908,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio3",		 909,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio2",		 910,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio1",		 911,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio0",		 912,	R8A7796_CLK_S3D4),

};

};





static const unsigned int r8a7796_crit_mod_clks[] __initconst = {

static const unsigned int r8a7796_crit_mod_clks[] __initconst = {