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Commit 8fe097a3 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Paul Walmsley
Browse files

ARM: DRA7: hwmod: Add reset data for PCIe 



Add PCIe reset data to PCIe hwmods on DRA7x.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
Reviewed-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 4965be1f

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+15 −0
Original line number Original line Diff line number Diff line
@@ -1531,29 +1531,44 @@ static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { 
};

};





/* pcie1 */

/* pcie1 */

static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {

	{ .name = "pcie", .rst_shift = 0 },

};



static struct omap_hwmod dra7xx_pciess1_hwmod = {

static struct omap_hwmod dra7xx_pciess1_hwmod = {

	.name		= "pcie1",

	.name		= "pcie1",

	.class		= &dra7xx_pciess_hwmod_class,

	.class		= &dra7xx_pciess_hwmod_class,

	.clkdm_name	= "pcie_clkdm",

	.clkdm_name	= "pcie_clkdm",

	.rst_lines	= dra7xx_pciess1_resets,

	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_pciess1_resets),

	.main_clk	= "l4_root_clk_div",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

	.prcm = {

		.omap4 = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,

			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,

			.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

			.modulemode   = MODULEMODE_SWCTRL,

		},

		},

	},

	},

};

};





/* pcie2 */

static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {

	{ .name = "pcie", .rst_shift = 1 },

};



/* pcie2 */

/* pcie2 */

static struct omap_hwmod dra7xx_pciess2_hwmod = {

static struct omap_hwmod dra7xx_pciess2_hwmod = {

	.name		= "pcie2",

	.name		= "pcie2",

	.class		= &dra7xx_pciess_hwmod_class,

	.class		= &dra7xx_pciess_hwmod_class,

	.clkdm_name	= "pcie_clkdm",

	.clkdm_name	= "pcie_clkdm",

	.rst_lines	= dra7xx_pciess2_resets,

	.rst_lines_cnt	= ARRAY_SIZE(dra7xx_pciess2_resets),

	.main_clk	= "l4_root_clk_div",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

	.prcm = {

		.omap4 = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,

			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,

			.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,

			.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

			.modulemode   = MODULEMODE_SWCTRL,

		},

		},

arch/arm/mach-omap2/prm7xx.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -360,6 +360,7 @@ 
/* PRM.L3INIT_PRM register offsets */

/* PRM.L3INIT_PRM register offsets */

#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000

#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000

#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET				0x0004

#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET				0x0004

#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET			0x0010

#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028

#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028

#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c

#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c

#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030

#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030