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Commit 8fcd5cd8 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Simplify CHV pipe A power well code 



The pipe A power well is the "disp2d" well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the checks for pipe A vs.
others and just assume it's always pipe A.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 60bfe44f

drivers/gpu/drm/i915/intel_runtime_pm.c

+20 −27
Original line number Diff line number Diff line
@@ -1042,19 +1042,18 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 
static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,

					struct i915_power_well *power_well)

{

	WARN_ON_ONCE(power_well->data != PIPE_A);



	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);

}



static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,

				       struct i915_power_well *power_well)

{

	WARN_ON_ONCE(power_well->data != PIPE_A &&

		     power_well->data != PIPE_B &&

		     power_well->data != PIPE_C);

	WARN_ON_ONCE(power_well->data != PIPE_A);



	chv_set_pipe_power_well(dev_priv, power_well, true);



	if (power_well->data == PIPE_A) {

	spin_lock_irq(&dev_priv->irq_lock);

	valleyview_enable_display_irqs(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);
@@ -1070,24 +1069,18 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 


	i915_redisable_vga_power_on(dev_priv->dev);

}

}



static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,

					struct i915_power_well *power_well)

{

	WARN_ON_ONCE(power_well->data != PIPE_A &&

		     power_well->data != PIPE_B &&

		     power_well->data != PIPE_C);

	WARN_ON_ONCE(power_well->data != PIPE_A);



	if (power_well->data == PIPE_A) {

	spin_lock_irq(&dev_priv->irq_lock);

	valleyview_disable_display_irqs(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);

	}



	chv_set_pipe_power_well(dev_priv, power_well, false);



	if (power_well->data == PIPE_A)

	vlv_power_sequencer_reset(dev_priv);

}