Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8fb9aeb7 authored by Abhilash Kesavan's avatar Abhilash Kesavan Committed by Tomasz Figa
Browse files

clk: samsung: exynos5250: Add MDMA0 clocks 



Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 3bf34666

Documentation/devicetree/bindings/clock/exynos5250-clock.txt

+2 −0
Original line number Diff line number Diff line
@@ -159,6 +159,8 @@ clock which they consume. 
  mixer			343

  hdmi			344

  g2d			345

  mdma0			346

  smmu_mdma0		347





   [Clock Muxes]

drivers/clk/samsung/clk-exynos5250.c

+4 −1
Original line number Diff line number Diff line
@@ -120,7 +120,8 @@ enum exynos5250_clks { 
	spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,

	hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,

	tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,

	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,

	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,

	smmu_mdma0,



	/* mux clocks */

	mout_hdmi = 1024,
@@ -492,6 +493,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 
	GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),

	GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),

	GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),

	GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),

	GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),

};



static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {