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Commit 8f90c7b6 authored by Gregory Bean's avatar Gregory Bean Committed by Daniel Walker
Browse files

msm: generialize IRQ to support multiple SOCs. 



irqs.h is specific to the MSM7x00 series devices.  Generalize
this in preparation to support more devices.

Signed-off-by: default avatarGregory Bean <gbean@codeaurora.org>
Signed-off-by: default avatarDavid Brown <davidb@codeaurora.org>
Signed-off-by: default avatarDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: default avatarAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
parent 0a8cff38

arch/arm/mach-msm/include/mach/irqs-7x00.h

0 → 100644
+75 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2007 Google, Inc.

 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.

 * Author: Brian Swetland <swetland@google.com>

 */



#ifndef __ASM_ARCH_MSM_IRQS_7X00_H

#define __ASM_ARCH_MSM_IRQS_7X00_H



/* MSM ARM11 Interrupt Numbers */

/* See 80-VE113-1 A, pp219-221     */



#define INT_A9_M2A_0         0

#define INT_A9_M2A_1         1

#define INT_A9_M2A_2         2

#define INT_A9_M2A_3         3

#define INT_A9_M2A_4         4

#define INT_A9_M2A_5         5

#define INT_A9_M2A_6         6

#define INT_GP_TIMER_EXP     7

#define INT_DEBUG_TIMER_EXP  8

#define INT_UART1            9

#define INT_UART2            10

#define INT_UART3            11

#define INT_UART1_RX         12

#define INT_UART2_RX         13

#define INT_UART3_RX         14

#define INT_USB_OTG          15

#define INT_MDDI_PRI         16

#define INT_MDDI_EXT         17

#define INT_MDDI_CLIENT      18

#define INT_MDP              19

#define INT_GRAPHICS         20

#define INT_ADM_AARM         21

#define INT_ADSP_A11         22

#define INT_ADSP_A9_A11      23

#define INT_SDC1_0           24

#define INT_SDC1_1           25

#define INT_SDC2_0           26

#define INT_SDC2_1           27

#define INT_KEYSENSE         28

#define INT_TCHSCRN_SSBI     29

#define INT_TCHSCRN1         30

#define INT_TCHSCRN2         31



#define INT_GPIO_GROUP1      (32 + 0)

#define INT_GPIO_GROUP2      (32 + 1)

#define INT_PWB_I2C          (32 + 2)

#define INT_SOFTRESET        (32 + 3)

#define INT_NAND_WR_ER_DONE  (32 + 4)

#define INT_NAND_OP_DONE     (32 + 5)

#define INT_PBUS_ARM11       (32 + 6)

#define INT_AXI_MPU_SMI      (32 + 7)

#define INT_AXI_MPU_EBI1     (32 + 8)

#define INT_AD_HSSD          (32 + 9)

#define INT_ARM11_PMU        (32 + 10)

#define INT_ARM11_DMA        (32 + 11)

#define INT_TSIF_IRQ         (32 + 12)

#define INT_UART1DM_IRQ      (32 + 13)

#define INT_UART1DM_RX       (32 + 14)

#define INT_USB_HS           (32 + 15)

#define INT_SDC3_0           (32 + 16)

#define INT_SDC3_1           (32 + 17)

#define INT_SDC4_0           (32 + 18)

#define INT_SDC4_1           (32 + 19)

#define INT_UART2DM_RX       (32 + 20)

#define INT_UART2DM_IRQ      (32 + 21)



/* 22-31 are reserved */



#define NR_MSM_IRQS 64

#define NR_GPIO_IRQS 122

#define NR_BOARD_IRQS 64



#endif

arch/arm/mach-msm/include/mach/irqs.h

+9 −67
Original line number Original line Diff line number Diff line 
/* arch/arm/mach-msm/include/mach/irqs.h

/*

 *

 * Copyright (C) 2007 Google, Inc.

 * Copyright (C) 2007 Google, Inc.

 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.

 * Author: Brian Swetland <swetland@google.com>

 * Author: Brian Swetland <swetland@google.com>

 *

 *

 * This software is licensed under the terms of the GNU General Public

 * This software is licensed under the terms of the GNU General Public
@@ -17,74 +17,16 @@ 
#ifndef __ASM_ARCH_MSM_IRQS_H

#ifndef __ASM_ARCH_MSM_IRQS_H

#define __ASM_ARCH_MSM_IRQS_H

#define __ASM_ARCH_MSM_IRQS_H





/* MSM ARM11 Interrupt Numbers */

/* See 80-VE113-1 A, pp219-221     */



#define INT_A9_M2A_0         0

#define INT_A9_M2A_1         1

#define INT_A9_M2A_2         2

#define INT_A9_M2A_3         3

#define INT_A9_M2A_4         4

#define INT_A9_M2A_5         5

#define INT_A9_M2A_6         6

#define INT_GP_TIMER_EXP     7

#define INT_DEBUG_TIMER_EXP  8

#define INT_UART1            9

#define INT_UART2            10

#define INT_UART3            11

#define INT_UART1_RX         12

#define INT_UART2_RX         13

#define INT_UART3_RX         14

#define INT_USB_OTG          15

#define INT_MDDI_PRI         16

#define INT_MDDI_EXT         17

#define INT_MDDI_CLIENT      18

#define INT_MDP              19

#define INT_GRAPHICS         20

#define INT_ADM_AARM         21

#define INT_ADSP_A11         22

#define INT_ADSP_A9_A11      23

#define INT_SDC1_0           24

#define INT_SDC1_1           25

#define INT_SDC2_0           26

#define INT_SDC2_1           27

#define INT_KEYSENSE         28

#define INT_TCHSCRN_SSBI     29

#define INT_TCHSCRN1         30

#define INT_TCHSCRN2         31



#define INT_GPIO_GROUP1      (32 + 0)

#define INT_GPIO_GROUP2      (32 + 1)

#define INT_PWB_I2C          (32 + 2)

#define INT_SOFTRESET        (32 + 3)

#define INT_NAND_WR_ER_DONE  (32 + 4)

#define INT_NAND_OP_DONE     (32 + 5)

#define INT_PBUS_ARM11       (32 + 6)

#define INT_AXI_MPU_SMI      (32 + 7)

#define INT_AXI_MPU_EBI1     (32 + 8)

#define INT_AD_HSSD          (32 + 9)

#define INT_ARM11_PMU        (32 + 10)

#define INT_ARM11_DMA        (32 + 11)

#define INT_TSIF_IRQ         (32 + 12)

#define INT_UART1DM_IRQ      (32 + 13)

#define INT_UART1DM_RX       (32 + 14)

#define INT_USB_HS           (32 + 15)

#define INT_SDC3_0           (32 + 16)

#define INT_SDC3_1           (32 + 17)

#define INT_SDC4_0           (32 + 18)

#define INT_SDC4_1           (32 + 19)

#define INT_UART2DM_RX       (32 + 20)

#define INT_UART2DM_IRQ      (32 + 21)



/* 22-31 are reserved */



#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))

#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))





#define NR_MSM_IRQS 64

#if defined(CONFIG_ARCH_MSM_ARM11)

#define NR_GPIO_IRQS 122

#include "irqs-7x00.h"

#define NR_BOARD_IRQS 64

#else

#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)

#error "Unknown architecture specification"

#endif





#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)

#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))

#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))

#define MSM_INT_TO_REG(base, irq) (base + irq / 32)





#endif
 
#endif