Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8f70920f authored by Stephen Hemminger's avatar Stephen Hemminger Committed by Jeff Garzik
Browse files

sky2: GPIO register 



The General Purpose I/O register is yet another hardware workaround
catchall. Enable workaround that vendor driver does to stay
but for bug compatiable.

Signed-off-by: default avatarStephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 451af335

drivers/net/sky2.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -230,6 +230,11 @@ static void sky2_power_on(struct sky2_hw *hw) 
		sky2_pci_write32(hw, PCI_DEV_REG5, reg);

		sky2_pci_write32(hw, PCI_DEV_REG5, reg);





		sky2_pci_write32(hw, PCI_CFG_REG_1, 0);

		sky2_pci_write32(hw, PCI_CFG_REG_1, 0);



		/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */

		reg = sky2_read32(hw, B2_GP_IO);

		reg |= GLB_GPIO_STAT_RACE_DIS;

		sky2_write32(hw, B2_GP_IO, reg);

	}

	}

}

}

drivers/net/sky2.h

+14 −0
Original line number Original line Diff line number Diff line
@@ -441,6 +441,20 @@ enum { 
	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */

	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */

};

};





/* 	B2_GPIO */

enum {

	GLB_GPIO_CLK_DEB_ENA = 1<<31,	/* Clock Debug Enable */

	GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */



	GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */

	GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */

	GLB_GPIO_STAT_RACE_DIS	= 1<<13, /* Status Race Disable */

	GLB_GPIO_TEST_SEL_MSK	= 3<<11, /* Testmode Select */

	GLB_GPIO_TEST_SEL_BASE	= 1<<11,

	GLB_GPIO_RAND_ENA	= 1<<10, /* Random Enable */

	GLB_GPIO_RAND_BIT_1	= 1<<9,  /* Random Bit 1 */

};



/*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */

/*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */

enum {

enum {

	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */

	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */