Commit 8eeab81c authored Jul 04, 2016 by James Hogan Committed by Paolo Bonzini Jul 05, 2016

MIPS: KVM: Decode RDHWR more strictly

When KVM emulates the RDHWR instruction, decode the instruction more
strictly. The rs field (bits 25:21) should be zero, as should bits 10:9.
Bits 8:6 is the register select field in MIPSr6, so we aren't strict
about those bits (no other operations should use that encoding space).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim KrÄmÃ¡Å™ <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

parent 5cc4aafc

arch/mips/kvm/emulate.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -2357,7 +2357,9 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
		}

		if (inst.r_format.opcode == spec3_op &&
		inst.r_format.func == rdhwr_op) {
		inst.r_format.func == rdhwr_op &&
		inst.r_format.rs == 0 &&
		(inst.r_format.re >> 3) == 0) {
		int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
		int rd = inst.r_format.rd;
		int rt = inst.r_format.rt;