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Commit 8ed5c062 authored by Thierry Reding's avatar Thierry Reding
Browse files

gpu: host1x: mipi: Fix clock lane register for DSI 



Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 83a3c223

drivers/gpu/host1x/mipi.c

+5 −5
Original line number Diff line number Diff line
@@ -52,8 +52,8 @@ 
#define MIPI_CAL_CONFIG_DSIC		0x10

#define MIPI_CAL_CONFIG_DSID		0x11



#define MIPI_CAL_CONFIG_DSIAB_CLK	0x19

#define MIPI_CAL_CONFIG_DSICD_CLK	0x1a

#define MIPI_CAL_CONFIG_DSIA_CLK	0x19

#define MIPI_CAL_CONFIG_DSIB_CLK	0x1a

#define MIPI_CAL_CONFIG_CSIAB_CLK	0x1b

#define MIPI_CAL_CONFIG_CSICD_CLK	0x1c

#define MIPI_CAL_CONFIG_CSIE_CLK	0x1d
@@ -327,8 +327,8 @@ static const struct tegra_mipi_pad tegra124_mipi_pads[] = { 
	{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },

	{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },

	{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK  },

	{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },

	{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },

	{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK  },

	{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK  },

};



static const struct tegra_mipi_soc tegra124_mipi_soc = {