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Commit 8e97b85a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-next' 



Vince Bridgers says:

====================
net: stmmac: Improve mcast/ucast filter for snps

This patch series adds Synopsys specific bindings for the Synopsys EMAC
filter characteristics since those are implementation dependent. The
multicast and unicast filtering code was improved to handle different
configuration variations based on device tree settings.

I verified the operation of the multicast and unicast filters through
Synopsys support as requested during the V1 review, and tested the GMAC
configuration on an Altera Cyclone 5 SOC (which supports 256 multicast
bins and 128 Unicast addresses). The 10/100 variant of this driver
modification was not tested, although it was compile tested. I shared
the email thread results of the investigation through Synopsys with the
stmmac maintainer.

V4: Remove patch from series that addressed a sparse issue from a
    down rev'd version of sparse that does not show up in the
    latest version of sparse.
V3: Break up the patch into interface and functional change patches
    per review comments
V2: Confirm with Synopsys methods to determine number of Multicast bins
    and Unicast address filter entries per first round review comments.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a173e550 3b57de95

Documentation/devicetree/bindings/net/stmmac.txt

+6 −0
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ Required properties: 
- snps,force_sf_dma_mode	Force DMA to use the Store and Forward

				mode for both tx and rx. This flag is

				ignored if force_thresh_dma_mode is set.

- snps,multicast-filter-bins:	Number of multicast filter hash bins

				supported by this device instance

- snps,perfect-filter-entries:	Number of perfect filter entries supported

				by this device instance



Optional properties:

- resets: Should contain a phandle to the STMMAC reset signal, if any
@@ -47,6 +51,8 @@ Examples: 
		mac-address = [000000000000]; /* Filled in by U-Boot */

		max-frame-size = <3800>;

		phy-mode = "gmii";

		snps,multicast-filter-bins = <256>;

		snps,perfect-filter-entries = <128>;

		clocks = <&clock>;

		clock-names = "stmmaceth">;

	};

arch/arm/boot/dts/socfpga.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -486,6 +486,8 @@ 
			clock-names = "stmmaceth";

			resets = <&rst EMAC0_RESET>;

			reset-names = "stmmaceth";

			snps,multicast-filter-bins = <256>;

			snps,perfect-filter-entries = <128>;

			status = "disabled";

		};
@@ -500,6 +502,8 @@ 
			clock-names = "stmmaceth";

			resets = <&rst EMAC1_RESET>;

			reset-names = "stmmaceth";

			snps,multicast-filter-bins = <256>;

			snps,perfect-filter-entries = <128>;

			status = "disabled";

		};

drivers/net/ethernet/stmicro/stmmac/common.h

+27 −20
Original line number Diff line number Diff line
@@ -368,34 +368,36 @@ struct stmmac_dma_ops { 
	void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);

};



struct mac_device_info;



struct stmmac_ops {

	/* MAC core initialization */

	void (*core_init) (void __iomem *ioaddr, int mtu);

	void (*core_init)(struct mac_device_info *hw, int mtu);

	/* Enable and verify that the IPC module is supported */

	int (*rx_ipc) (void __iomem *ioaddr);

	int (*rx_ipc)(struct mac_device_info *hw);

	/* Dump MAC registers */

	void (*dump_regs) (void __iomem *ioaddr);

	void (*dump_regs)(struct mac_device_info *hw);

	/* Handle extra events on specific interrupts hw dependent */

	int (*host_irq_status) (void __iomem *ioaddr,

	int (*host_irq_status)(struct mac_device_info *hw,

			       struct stmmac_extra_stats *x);

	/* Multicast filter setting */

	void (*set_filter) (struct net_device *dev, int id);

	void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);

	/* Flow control setting */

	void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,

	void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,

			  unsigned int fc, unsigned int pause_time);

	/* Set power management mode (e.g. magic frame) */

	void (*pmt) (void __iomem *ioaddr, unsigned long mode);

	void (*pmt)(struct mac_device_info *hw, unsigned long mode);

	/* Set/Get Unicast MAC addresses */

	void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,

	void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,

			      unsigned int reg_n);

	void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,

	void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,

			      unsigned int reg_n);

	void (*set_eee_mode) (void __iomem *ioaddr);

	void (*reset_eee_mode) (void __iomem *ioaddr);

	void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);

	void (*set_eee_pls) (void __iomem *ioaddr, int link);

	void (*ctrl_ane) (void __iomem *ioaddr, bool restart);

	void (*get_adv) (void __iomem *ioaddr, struct rgmii_adv *adv);

	void (*set_eee_mode)(struct mac_device_info *hw);

	void (*reset_eee_mode)(struct mac_device_info *hw);

	void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);

	void (*set_eee_pls)(struct mac_device_info *hw, int link);

	void (*ctrl_ane)(struct mac_device_info *hw, bool restart);

	void (*get_adv)(struct mac_device_info *hw, struct rgmii_adv *adv);

};



struct stmmac_hwtimestamp {
@@ -439,9 +441,14 @@ struct mac_device_info { 
	struct mii_regs mii;	/* MII register Addresses */

	struct mac_link link;

	unsigned int synopsys_uid;

	void __iomem *pcsr;     /* vpointer to device CSRs */

	int multicast_filter_bins;

	int unicast_filter_entries;

	int mcast_bits_log2;

};



struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);

struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,

					int perfect_uc_entries);

struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);



void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+2 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ enum power_event { 
				(reg * 8))

#define GMAC_ADDR_LOW(reg)	(((reg > 15) ? 0x00000804 : 0x00000044) + \

				(reg * 8))

#define GMAC_MAX_PERFECT_ADDRESSES	32

#define GMAC_MAX_PERFECT_ADDRESSES	1



/* PCS registers (AN/TBI/SGMII/RGMII) offset */

#define GMAC_AN_CTRL	0x000000c0	/* AN control */
@@ -261,6 +261,7 @@ enum rtc_control { 
#define GMAC_MMC_RX_INTR   0x104

#define GMAC_MMC_TX_INTR   0x108

#define GMAC_MMC_RX_CSUM_OFFLOAD   0x208

#define GMAC_EXTHASH_BASE  0x500



extern const struct stmmac_dma_ops dwmac1000_dma_ops;

#endif /* __DWMAC1000_H__ */

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+90 −41
Original line number Diff line number Diff line
@@ -32,8 +32,9 @@ 
#include <asm/io.h>

#include "dwmac1000.h"



static void dwmac1000_core_init(void __iomem *ioaddr, int mtu)

static void dwmac1000_core_init(struct mac_device_info *hw, int mtu)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 value = readl(ioaddr + GMAC_CONTROL);

	value |= GMAC_CORE_INIT;

	if (mtu > 1500)
@@ -52,8 +53,9 @@ static void dwmac1000_core_init(void __iomem *ioaddr, int mtu) 
#endif

}



static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr)

static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 value = readl(ioaddr + GMAC_CONTROL);



	value |= GMAC_CONTROL_IPC;
@@ -64,8 +66,9 @@ static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr) 
	return !!(value & GMAC_CONTROL_IPC);

}



static void dwmac1000_dump_regs(void __iomem *ioaddr)

static void dwmac1000_dump_regs(struct mac_device_info *hw)

{

	void __iomem *ioaddr = hw->pcsr;

	int i;

	pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
@@ -76,69 +79,98 @@ static void dwmac1000_dump_regs(void __iomem *ioaddr) 
	}

}



static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,

static void dwmac1000_set_umac_addr(struct mac_device_info *hw,

				    unsigned char *addr,

				    unsigned int reg_n)

{

	void __iomem *ioaddr = hw->pcsr;

	stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),

			    GMAC_ADDR_LOW(reg_n));

}



static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,

static void dwmac1000_get_umac_addr(struct mac_device_info *hw,

				    unsigned char *addr,

				    unsigned int reg_n)

{

	void __iomem *ioaddr = hw->pcsr;

	stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),

			    GMAC_ADDR_LOW(reg_n));

}



static void dwmac1000_set_filter(struct net_device *dev, int id)

static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,

				 int mcbitslog2)

{

	int numhashregs, regs;



	switch (mcbitslog2) {

	case 6:

		writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);

		writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);

		return;

		break;

	case 7:

		numhashregs = 4;

		break;

	case 8:

		numhashregs = 8;

		break;

	default:

		pr_debug("STMMAC: err in setting mulitcast filter\n");

		return;

		break;

	}

	for (regs = 0; regs < numhashregs; regs++)

		writel(mcfilterbits[regs],

		       ioaddr + GMAC_EXTHASH_BASE + regs * 4);

}



static void dwmac1000_set_filter(struct mac_device_info *hw,

				 struct net_device *dev)

{

	void __iomem *ioaddr = (void __iomem *)dev->base_addr;

	unsigned int value = 0;

	unsigned int perfect_addr_number;

	unsigned int perfect_addr_number = hw->unicast_filter_entries;

	u32 mc_filter[2];

	int mcbitslog2 = hw->mcast_bits_log2;



	pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,

		 netdev_mc_count(dev), netdev_uc_count(dev));



	if (dev->flags & IFF_PROMISC)

	memset(mc_filter, 0, sizeof(mc_filter));



	if (dev->flags & IFF_PROMISC) {

		value = GMAC_FRAME_FILTER_PR;

	else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)

		 || (dev->flags & IFF_ALLMULTI)) {

	} else if (dev->flags & IFF_ALLMULTI) {

		value = GMAC_FRAME_FILTER_PM;	/* pass all multi */

		writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);

		writel(0xffffffff, ioaddr + GMAC_HASH_LOW);

	} else if (!netdev_mc_empty(dev)) {

		u32 mc_filter[2];

		struct netdev_hw_addr *ha;



		/* Hash filter for multicast */

		value = GMAC_FRAME_FILTER_HMC;



		memset(mc_filter, 0, sizeof(mc_filter));

		netdev_for_each_mc_addr(ha, dev) {

			/* The upper 6 bits of the calculated CRC are used to

			 * index the contens of the hash table

			/* The upper n bits of the calculated CRC are used to

			 * index the contents of the hash table. The number of

			 * bits used depends on the hardware configuration

			 * selected at core configuration time.

			 */

			int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;

			int bit_nr = bitrev32(~crc32_le(~0, ha->addr,

					      ETH_ALEN)) >>

					      (32 - mcbitslog2);

			/* The most significant bit determines the register to

			 * use (H/L) while the other 5 bits determine the bit

			 * within the register.

			 */

			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);

		}

		writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);

		writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);

	}



	/* Extra 16 regs are available in cores newer than the 3.40. */

	if (id > DWMAC_CORE_3_40)

		perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES;

	else

		perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES / 2;

	dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);



	/* Handle multiple unicast addresses (perfect filtering) */

	if (netdev_uc_count(dev) > perfect_addr_number)

		/* Switch to promiscuous mode if more than 16 addrs

		 * are required

		/* Switch to promiscuous mode if more than unicast

		 * addresses are requested than supported by hardware.

		 */

		value |= GMAC_FRAME_FILTER_PR;

	else {
@@ -146,7 +178,9 @@ static void dwmac1000_set_filter(struct net_device *dev, int id) 
		struct netdev_hw_addr *ha;



		netdev_for_each_uc_addr(ha, dev) {

			dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);

			stmmac_get_mac_addr(ioaddr, ha->addr,

					    GMAC_ADDR_HIGH(reg),

					    GMAC_ADDR_LOW(reg));

			reg++;

		}

	}
@@ -156,15 +190,13 @@ static void dwmac1000_set_filter(struct net_device *dev, int id) 
	value |= GMAC_FRAME_FILTER_RA;

#endif

	writel(value, ioaddr + GMAC_FRAME_FILTER);



	pr_debug("\tFilter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",

		 readl(ioaddr + GMAC_FRAME_FILTER),

		 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));

}



static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,



static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,

				unsigned int fc, unsigned int pause_time)

{

	void __iomem *ioaddr = hw->pcsr;

	unsigned int flow = 0;



	pr_debug("GMAC Flow-Control:\n");
@@ -185,8 +217,9 @@ static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex, 
	writel(flow, ioaddr + GMAC_FLOW_CTRL);

}



static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)

static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)

{

	void __iomem *ioaddr = hw->pcsr;

	unsigned int pmt = 0;



	if (mode & WAKE_MAGIC) {
@@ -201,9 +234,10 @@ static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode) 
	writel(pmt, ioaddr + GMAC_PMT);

}



static int dwmac1000_irq_status(void __iomem *ioaddr,

static int dwmac1000_irq_status(struct mac_device_info *hw,

				struct stmmac_extra_stats *x)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);

	int ret = 0;
@@ -268,8 +302,9 @@ static int dwmac1000_irq_status(void __iomem *ioaddr, 
	return ret;

}



static void dwmac1000_set_eee_mode(void __iomem *ioaddr)

static void dwmac1000_set_eee_mode(struct mac_device_info *hw)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 value;



	/* Enable the link status receive on RGMII, SGMII ore SMII
@@ -281,8 +316,9 @@ static void dwmac1000_set_eee_mode(void __iomem *ioaddr) 
	writel(value, ioaddr + LPI_CTRL_STATUS);

}



static void dwmac1000_reset_eee_mode(void __iomem *ioaddr)

static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 value;



	value = readl(ioaddr + LPI_CTRL_STATUS);
@@ -290,8 +326,9 @@ static void dwmac1000_reset_eee_mode(void __iomem *ioaddr) 
	writel(value, ioaddr + LPI_CTRL_STATUS);

}



static void dwmac1000_set_eee_pls(void __iomem *ioaddr, int link)

static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 value;



	value = readl(ioaddr + LPI_CTRL_STATUS);
@@ -304,8 +341,9 @@ static void dwmac1000_set_eee_pls(void __iomem *ioaddr, int link) 
	writel(value, ioaddr + LPI_CTRL_STATUS);

}



static void dwmac1000_set_eee_timer(void __iomem *ioaddr, int ls, int tw)

static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)

{

	void __iomem *ioaddr = hw->pcsr;

	int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);



	/* Program the timers in the LPI timer control register:
@@ -318,8 +356,9 @@ static void dwmac1000_set_eee_timer(void __iomem *ioaddr, int ls, int tw) 
	writel(value, ioaddr + LPI_TIMER_CTRL);

}



static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool restart)

static void dwmac1000_ctrl_ane(struct mac_device_info *hw, bool restart)

{

	void __iomem *ioaddr = hw->pcsr;

	/* auto negotiation enable and External Loopback enable */

	u32 value = GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_ELE;
@@ -329,8 +368,9 @@ static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool restart) 
	writel(value, ioaddr + GMAC_AN_CTRL);

}



static void dwmac1000_get_adv(void __iomem *ioaddr, struct rgmii_adv *adv)

static void dwmac1000_get_adv(struct mac_device_info *hw, struct rgmii_adv *adv)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 value = readl(ioaddr + GMAC_ANE_ADV);



	if (value & GMAC_ANE_FD)
@@ -368,7 +408,8 @@ static const struct stmmac_ops dwmac1000_ops = { 
	.get_adv = dwmac1000_get_adv,

};



struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)

struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,

					int perfect_uc_entries)

{

	struct mac_device_info *mac;

	u32 hwid = readl(ioaddr + GMAC_VERSION);
@@ -377,6 +418,14 @@ struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr) 
	if (!mac)

		return NULL;



	mac->pcsr = ioaddr;

	mac->multicast_filter_bins = mcbins;

	mac->unicast_filter_entries = perfect_uc_entries;

	mac->mcast_bits_log2 = 0;



	if (mac->multicast_filter_bins)

		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);



	mac->mac = &dwmac1000_ops;

	mac->dma = &dwmac1000_dma_ops;