Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8e711e1a authored by David Zhang's avatar David Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add Fiji support to SMC and DPM (v2) 



v2: agd5f: prepare for release

Signed-off-by: default avatarDavid Zhang <david1.zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent d1c4dcfb

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ amdgpu-y += \ 
	amdgpu_dpm.o \

	cz_smc.o cz_dpm.o \

	tonga_smc.o tonga_dpm.o \

	fiji_smc.o fiji_dpm.o \

	iceland_smc.o iceland_dpm.o



# add DCE block

drivers/gpu/drm/amd/amdgpu/fiji_dpm.c

0 → 100644
+181 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include <linux/firmware.h>

#include "drmP.h"

#include "amdgpu.h"

#include "fiji_smumgr.h"



MODULE_FIRMWARE("amdgpu/fiji_smc.bin");



static void fiji_dpm_set_funcs(struct amdgpu_device *adev);



static int fiji_dpm_early_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	fiji_dpm_set_funcs(adev);



	return 0;

}



static int fiji_dpm_init_microcode(struct amdgpu_device *adev)

{

	char fw_name[30] = "amdgpu/fiji_smc.bin";

	int err;



	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);

	if (err)

		goto out;

	err = amdgpu_ucode_validate(adev->pm.fw);



out:

	if (err) {

		DRM_ERROR("Failed to load firmware \"%s\"", fw_name);

		release_firmware(adev->pm.fw);

		adev->pm.fw = NULL;

	}

	return err;

}



static int fiji_dpm_sw_init(void *handle)

{

	int ret;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	ret = fiji_dpm_init_microcode(adev);

	if (ret)

		return ret;



	return 0;

}



static int fiji_dpm_sw_fini(void *handle)

{

	return 0;

}



static int fiji_dpm_hw_init(void *handle)

{

	int ret;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	mutex_lock(&adev->pm.mutex);



	ret = fiji_smu_init(adev);

	if (ret) {

		DRM_ERROR("SMU initialization failed\n");

		goto fail;

	}



	ret = fiji_smu_start(adev);

	if (ret) {

		DRM_ERROR("SMU start failed\n");

		goto fail;

	}



	mutex_unlock(&adev->pm.mutex);

	return 0;



fail:

	adev->firmware.smu_load = false;

	mutex_unlock(&adev->pm.mutex);

	return -EINVAL;

}



static int fiji_dpm_hw_fini(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	mutex_lock(&adev->pm.mutex);

	fiji_smu_fini(adev);

	mutex_unlock(&adev->pm.mutex);

	return 0;

}



static int fiji_dpm_suspend(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	fiji_dpm_hw_fini(adev);



	return 0;

}



static int fiji_dpm_resume(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	fiji_dpm_hw_init(adev);



	return 0;

}



static int fiji_dpm_set_clockgating_state(void *handle,

			enum amd_clockgating_state state)

{

	return 0;

}



static int fiji_dpm_set_powergating_state(void *handle,

			enum amd_powergating_state state)

{

	return 0;

}



const struct amd_ip_funcs fiji_dpm_ip_funcs = {

	.early_init = fiji_dpm_early_init,

	.late_init = NULL,

	.sw_init = fiji_dpm_sw_init,

	.sw_fini = fiji_dpm_sw_fini,

	.hw_init = fiji_dpm_hw_init,

	.hw_fini = fiji_dpm_hw_fini,

	.suspend = fiji_dpm_suspend,

	.resume = fiji_dpm_resume,

	.is_idle = NULL,

	.wait_for_idle = NULL,

	.soft_reset = NULL,

	.print_status = NULL,

	.set_clockgating_state = fiji_dpm_set_clockgating_state,

	.set_powergating_state = fiji_dpm_set_powergating_state,

};



static const struct amdgpu_dpm_funcs fiji_dpm_funcs = {

	.get_temperature = NULL,

	.pre_set_power_state = NULL,

	.set_power_state = NULL,

	.post_set_power_state = NULL,

	.display_configuration_changed = NULL,

	.get_sclk = NULL,

	.get_mclk = NULL,

	.print_power_state = NULL,

	.debugfs_print_current_performance_level = NULL,

	.force_performance_level = NULL,

	.vblank_too_short = NULL,

	.powergate_uvd = NULL,

};



static void fiji_dpm_set_funcs(struct amdgpu_device *adev)

{

	if (NULL == adev->pm.funcs)

		adev->pm.funcs = &fiji_dpm_funcs;

}

drivers/gpu/drm/amd/amdgpu/fiji_ppsmc.h

0 → 100644
+182 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef FIJI_PP_SMC_H

#define FIJI_PP_SMC_H



#pragma pack(push, 1)



#define PPSMC_SWSTATE_FLAG_DC                           0x01

#define PPSMC_SWSTATE_FLAG_UVD                          0x02

#define PPSMC_SWSTATE_FLAG_VCE                          0x04



#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00

#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01

#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff



#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01

#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02

#define PPSMC_SYSTEMFLAG_GDDR5                          0x04



#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08



#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10

#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20



#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07

#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08



#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00

#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01



#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01

#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02

#define PPSMC_DPM2FLAGS_OCP                             0x04



#define PPSMC_DISPLAY_WATERMARK_LOW                     0

#define PPSMC_DISPLAY_WATERMARK_HIGH                    1



#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    		0x01

#define PPSMC_STATEFLAG_POWERBOOST         		0x02

#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 		0x04

#define PPSMC_STATEFLAG_POWERSHIFT         		0x08

#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   		0x10

#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 		0x20

#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   		0x40



#define FDO_MODE_HARDWARE 0

#define FDO_MODE_PIECE_WISE_LINEAR 1



enum FAN_CONTROL {

	FAN_CONTROL_FUZZY,

	FAN_CONTROL_TABLE

};



//Gemini Modes

#define PPSMC_GeminiModeNone   0  //Single GPU board

#define PPSMC_GeminiModeMaster 1  //Master GPU on a Gemini board

#define PPSMC_GeminiModeSlave  2  //Slave GPU on a Gemini board



#define PPSMC_Result_OK             			((uint16_t)0x01)

#define PPSMC_Result_NoMore         			((uint16_t)0x02)

#define PPSMC_Result_NotNow         			((uint16_t)0x03)

#define PPSMC_Result_Failed         			((uint16_t)0xFF)

#define PPSMC_Result_UnknownCmd     			((uint16_t)0xFE)

#define PPSMC_Result_UnknownVT      			((uint16_t)0xFD)



typedef uint16_t PPSMC_Result;



#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))



#define PPSMC_MSG_Halt                      		((uint16_t)0x10)

#define PPSMC_MSG_Resume                    		((uint16_t)0x11)

#define PPSMC_MSG_EnableDPMLevel            		((uint16_t)0x12)

#define PPSMC_MSG_ZeroLevelsDisabled        		((uint16_t)0x13)

#define PPSMC_MSG_OneLevelsDisabled         		((uint16_t)0x14)

#define PPSMC_MSG_TwoLevelsDisabled         		((uint16_t)0x15)

#define PPSMC_MSG_EnableThermalInterrupt    		((uint16_t)0x16)

#define PPSMC_MSG_RunningOnAC               		((uint16_t)0x17)

#define PPSMC_MSG_LevelUp                   		((uint16_t)0x18)

#define PPSMC_MSG_LevelDown                 		((uint16_t)0x19)

#define PPSMC_MSG_ResetDPMCounters          		((uint16_t)0x1a)

#define PPSMC_MSG_SwitchToSwState           		((uint16_t)0x20)

#define PPSMC_MSG_SwitchToSwStateLast       		((uint16_t)0x3f)

#define PPSMC_MSG_SwitchToInitialState      		((uint16_t)0x40)

#define PPSMC_MSG_NoForcedLevel             		((uint16_t)0x41)

#define PPSMC_MSG_ForceHigh                 		((uint16_t)0x42)

#define PPSMC_MSG_ForceMediumOrHigh         		((uint16_t)0x43)

#define PPSMC_MSG_SwitchToMinimumPower      		((uint16_t)0x51)

#define PPSMC_MSG_ResumeFromMinimumPower    		((uint16_t)0x52)

#define PPSMC_MSG_EnableCac                 		((uint16_t)0x53)

#define PPSMC_MSG_DisableCac                		((uint16_t)0x54)

#define PPSMC_DPMStateHistoryStart          		((uint16_t)0x55)

#define PPSMC_DPMStateHistoryStop           		((uint16_t)0x56)

#define PPSMC_CACHistoryStart               		((uint16_t)0x57)

#define PPSMC_CACHistoryStop                		((uint16_t)0x58)

#define PPSMC_TDPClampingActive             		((uint16_t)0x59)

#define PPSMC_TDPClampingInactive           		((uint16_t)0x5A)

#define PPSMC_StartFanControl               		((uint16_t)0x5B)

#define PPSMC_StopFanControl                		((uint16_t)0x5C)

#define PPSMC_NoDisplay                     		((uint16_t)0x5D)

#define PPSMC_HasDisplay                    		((uint16_t)0x5E)

#define PPSMC_MSG_UVDPowerOFF               		((uint16_t)0x60)

#define PPSMC_MSG_UVDPowerON                		((uint16_t)0x61)

#define PPSMC_MSG_EnableULV                 		((uint16_t)0x62)

#define PPSMC_MSG_DisableULV                		((uint16_t)0x63)

#define PPSMC_MSG_EnterULV                  		((uint16_t)0x64)

#define PPSMC_MSG_ExitULV                   		((uint16_t)0x65)

#define PPSMC_PowerShiftActive              		((uint16_t)0x6A)

#define PPSMC_PowerShiftInactive            		((uint16_t)0x6B)

#define PPSMC_OCPActive                     		((uint16_t)0x6C)

#define PPSMC_OCPInactive                   		((uint16_t)0x6D)

#define PPSMC_CACLongTermAvgEnable          		((uint16_t)0x6E)

#define PPSMC_CACLongTermAvgDisable         		((uint16_t)0x6F)

#define PPSMC_MSG_InferredStateSweep_Start  		((uint16_t)0x70)

#define PPSMC_MSG_InferredStateSweep_Stop   		((uint16_t)0x71)

#define PPSMC_MSG_SwitchToLowestInfState    		((uint16_t)0x72)

#define PPSMC_MSG_SwitchToNonInfState       		((uint16_t)0x73)

#define PPSMC_MSG_AllStateSweep_Start       		((uint16_t)0x74)

#define PPSMC_MSG_AllStateSweep_Stop        		((uint16_t)0x75)

#define PPSMC_MSG_SwitchNextLowerInfState   		((uint16_t)0x76)

#define PPSMC_MSG_SwitchNextHigherInfState  		((uint16_t)0x77)

#define PPSMC_MSG_MclkRetrainingTest        		((uint16_t)0x78)

#define PPSMC_MSG_ForceTDPClamping          		((uint16_t)0x79)

#define PPSMC_MSG_CollectCAC_PowerCorreln   		((uint16_t)0x7A)

#define PPSMC_MSG_CollectCAC_WeightCalib    		((uint16_t)0x7B)

#define PPSMC_MSG_CollectCAC_SQonly         		((uint16_t)0x7C)

#define PPSMC_MSG_CollectCAC_TemperaturePwr 		((uint16_t)0x7D)

#define PPSMC_MSG_ExtremitiesTest_Start     		((uint16_t)0x7E)

#define PPSMC_MSG_ExtremitiesTest_Stop      		((uint16_t)0x7F)

#define PPSMC_FlushDataCache                		((uint16_t)0x80)

#define PPSMC_FlushInstrCache               		((uint16_t)0x81)

#define PPSMC_MSG_SetEnabledLevels          		((uint16_t)0x82)

#define PPSMC_MSG_SetForcedLevels           		((uint16_t)0x83)

#define PPSMC_MSG_ResetToDefaults           		((uint16_t)0x84)

#define PPSMC_MSG_SetForcedLevelsAndJump    		((uint16_t)0x85)

#define PPSMC_MSG_SetCACHistoryMode         		((uint16_t)0x86)

#define PPSMC_MSG_EnableDTE                 		((uint16_t)0x87)

#define PPSMC_MSG_DisableDTE                		((uint16_t)0x88)

#define PPSMC_MSG_SmcSpaceSetAddress        		((uint16_t)0x89)

#define PPSMC_MSG_SmcSpaceWriteDWordInc     		((uint16_t)0x8A)

#define PPSMC_MSG_SmcSpaceWriteWordInc      		((uint16_t)0x8B)

#define PPSMC_MSG_SmcSpaceWriteByteInc      		((uint16_t)0x8C)



#define PPSMC_MSG_BREAK                     		((uint16_t)0xF8)



#define PPSMC_MSG_Test                      		((uint16_t)0x100)

#define PPSMC_MSG_DRV_DRAM_ADDR_HI            		((uint16_t)0x250)

#define PPSMC_MSG_DRV_DRAM_ADDR_LO            		((uint16_t)0x251)

#define PPSMC_MSG_SMU_DRAM_ADDR_HI            		((uint16_t)0x252)

#define PPSMC_MSG_SMU_DRAM_ADDR_LO            		((uint16_t)0x253)

#define PPSMC_MSG_LoadUcodes                  		((uint16_t)0x254)



typedef uint16_t PPSMC_Msg;



#define PPSMC_EVENT_STATUS_THERMAL          		0x00000001

#define PPSMC_EVENT_STATUS_REGULATORHOT     		0x00000002

#define PPSMC_EVENT_STATUS_DC               		0x00000004

#define PPSMC_EVENT_STATUS_GPIO17           		0x00000008



#pragma pack(pop)



#endif

drivers/gpu/drm/amd/amdgpu/fiji_smc.c

0 → 100644
+853 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/fiji_smumgr.h

0 → 100644
+42 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef FIJI_SMUMGR_H

#define FIJI_SMUMGR_H



#include "fiji_ppsmc.h"



int fiji_smu_init(struct amdgpu_device *adev);

int fiji_smu_fini(struct amdgpu_device *adev);

int fiji_smu_start(struct amdgpu_device *adev);



struct fiji_smu_private_data

{

	uint8_t *header;

	uint32_t smu_buffer_addr_high;

	uint32_t smu_buffer_addr_low;

	uint32_t header_addr_high;

	uint32_t header_addr_low;

};



#endif