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Commit 8d79c349 authored by Eric Anholt's avatar Eric Anholt Committed by Daniel Vetter
Browse files

drm/i915: Remove the MI_FLUSH_ENABLE setting. 



We have always been using the wrong bit -- it's bit 12.  However, the
bit also doesn't do anything -- hardware has always accepted the
MI_FLUSH command even when it was specced not to.

Given that there is only one MI_FLUSH emitted in all of the driver
stack on gen6+ (in i965_video.c of the 2d driver, and it should be
using other code to do its flush instead), just remove the MI_FLUSH
enable instead of trying to fix it.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8e636784

drivers/gpu/drm/i915/intel_ringbuffer.c

+0 −2
Original line number Diff line number Diff line
@@ -399,8 +399,6 @@ static int init_render_ring(struct intel_ring_buffer *ring) 


	if (INTEL_INFO(dev)->gen > 3) {

		int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;

		if (IS_GEN6(dev) || IS_GEN7(dev))

			mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;

		I915_WRITE(MI_MODE, mode);

		if (IS_GEN7(dev))

			I915_WRITE(GFX_MODE_GEN7,