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Commit 8d4d9f52 authored by Rob Herring's avatar Rob Herring Committed by Mike Turquette
Browse files

clk: add highbank clock support 



This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.

Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
[mturquette@linaro.org: fixed up invalid writes to const struct member]
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 260b6aa0

Documentation/devicetree/bindings/clock/calxeda.txt

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+17 −0
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Device Tree Clock bindings for Calxeda highbank platform



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be one of the following:

	"calxeda,hb-pll-clock" - for a PLL clock

	"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the

		A9 clock.

	"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.

	"calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.

- reg : shall be the control register offset from SYSREGs base for the clock.

- clocks : shall be the input parent clock phandle for the clock. This is

	either an oscillator or a pll output.

- #clock-cells : from common clock binding; shall be set to 0.

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -352,6 +352,7 @@ config ARCH_HIGHBANK 
	select ARM_TIMER_SP804

	select CACHE_L2X0

	select CLKDEV_LOOKUP

	select COMMON_CLK

	select CPU_V7

	select GENERIC_CLOCKEVENTS

	select HAVE_ARM_SCU

arch/arm/boot/dts/highbank.dts

+90 −1
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Calxeda, Inc.

 * Copyright 2011-2012 Calxeda, Inc.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,7 @@ 
	compatible = "calxeda,highbank";

	#address-cells = <1>;

	#size-cells = <1>;

	clock-ranges;



	cpus {

		#address-cells = <1>;
@@ -33,24 +34,32 @@ 
			compatible = "arm,cortex-a9";

			reg = <0>;

			next-level-cache = <&L2>;

			clocks = <&a9pll>;

			clock-names = "cpu";

		};



		cpu@1 {

			compatible = "arm,cortex-a9";

			reg = <1>;

			next-level-cache = <&L2>;

			clocks = <&a9pll>;

			clock-names = "cpu";

		};



		cpu@2 {

			compatible = "arm,cortex-a9";

			reg = <2>;

			next-level-cache = <&L2>;

			clocks = <&a9pll>;

			clock-names = "cpu";

		};



		cpu@3 {

			compatible = "arm,cortex-a9";

			reg = <3>;

			next-level-cache = <&L2>;

			clocks = <&a9pll>;

			clock-names = "cpu";

		};

	};
@@ -75,12 +84,14 @@ 
			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xfff10600 0x20>;

			interrupts = <1 13 0xf01>;

			clocks = <&a9periphclk>;

		};



		watchdog@fff10620 {

			compatible = "arm,cortex-a9-twd-wdt";

			reg = <0xfff10620 0x20>;

			interrupts = <1 14 0xf01>;

			clocks = <&a9periphclk>;

		};



		intc: interrupt-controller@fff11000 {
@@ -116,12 +127,15 @@ 
			compatible = "calxeda,hb-sdhci";

			reg = <0xffe0e000 0x1000>;

			interrupts = <0 90 4>;

			clocks = <&eclk>;

		};



		ipc@fff20000 {

			compatible = "arm,pl320", "arm,primecell";

			reg = <0xfff20000 0x1000>;

			interrupts = <0 7 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpioe: gpio@fff30000 {
@@ -130,6 +144,8 @@ 
			gpio-controller;

			reg = <0xfff30000 0x1000>;

			interrupts = <0 14 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpiof: gpio@fff31000 {
@@ -138,6 +154,8 @@ 
			gpio-controller;

			reg = <0xfff31000 0x1000>;

			interrupts = <0 15 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpiog: gpio@fff32000 {
@@ -146,6 +164,8 @@ 
			gpio-controller;

			reg = <0xfff32000 0x1000>;

			interrupts = <0 16 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpioh: gpio@fff33000 {
@@ -154,24 +174,32 @@ 
			gpio-controller;

			reg = <0xfff33000 0x1000>;

			interrupts = <0 17 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		timer {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0xfff34000 0x1000>;

			interrupts = <0 18 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		rtc@fff35000 {

			compatible = "arm,pl031", "arm,primecell";

			reg = <0xfff35000 0x1000>;

			interrupts = <0 19 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		serial@fff36000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xfff36000 0x1000>;

			interrupts = <0 20 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		smic@fff3a000 {
@@ -186,12 +214,73 @@ 
		sregs@fff3c000 {

			compatible = "calxeda,hb-sregs";

			reg = <0xfff3c000 0x1000>;



			clocks {

				#address-cells = <1>;

				#size-cells = <0>;



				osc: oscillator {

					#clock-cells = <0>;

					compatible = "fixed-clock";

					clock-frequency = <33333000>;

				};



				ddrpll: ddrpll {

					#clock-cells = <0>;

					compatible = "calxeda,hb-pll-clock";

					clocks = <&osc>;

					reg = <0x108>;

				};



				a9pll: a9pll {

					#clock-cells = <0>;

					compatible = "calxeda,hb-pll-clock";

					clocks = <&osc>;

					reg = <0x100>;

				};



				a9periphclk: a9periphclk {

					#clock-cells = <0>;

					compatible = "calxeda,hb-a9periph-clock";

					clocks = <&a9pll>;

					reg = <0x104>;

				};



				a9bclk: a9bclk {

					#clock-cells = <0>;

					compatible = "calxeda,hb-a9bus-clock";

					clocks = <&a9pll>;

					reg = <0x104>;

				};



				emmcpll: emmcpll {

					#clock-cells = <0>;

					compatible = "calxeda,hb-pll-clock";

					clocks = <&osc>;

					reg = <0x10C>;

				};



				eclk: eclk {

					#clock-cells = <0>;

					compatible = "calxeda,hb-emmc-clock";

					clocks = <&emmcpll>;

					reg = <0x114>;

				};



				pclk: pclk {

					#clock-cells = <0>;

					compatible = "fixed-clock";

					clock-frequency = <150000000>;

				};

			};

		};



		dma@fff3d000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0xfff3d000 0x1000>;

			interrupts = <0 92 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		ethernet@fff50000 {

arch/arm/mach-highbank/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y					:= clock.o highbank.o system.o smc.o

obj-y					:= highbank.o system.o smc.o



plus_sec := $(call as-instr,.arch_extension sec,+sec)

AFLAGS_smc.o				:=-Wa,-march=armv7-a$(plus_sec)

arch/arm/mach-highbank/clock.c

deleted100644 → 0
+0 −62
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/*

 * Copyright 2011 Calxeda, Inc.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/errno.h>

#include <linux/clk.h>

#include <linux/clkdev.h>



struct clk {

	unsigned long rate;

};



int clk_enable(struct clk *clk)

{

	return 0;

}



void clk_disable(struct clk *clk)

{}



unsigned long clk_get_rate(struct clk *clk)

{

	return clk->rate;

}



long clk_round_rate(struct clk *clk, unsigned long rate)

{

	return clk->rate;

}



int clk_set_rate(struct clk *clk, unsigned long rate)

{

	return 0;

}



static struct clk eclk = { .rate = 200000000 };

static struct clk pclk = { .rate = 150000000 };



static struct clk_lookup lookups[] = {

	{ .clk = &pclk, .con_id = "apb_pclk", },

	{ .clk = &pclk, .dev_id = "sp804", },

	{ .clk = &eclk, .dev_id = "ffe0e000.sdhci", },

	{ .clk = &pclk, .dev_id = "fff36000.serial", },

};



void __init highbank_clocks_init(void)

{

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

}