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Commit 8d41794c authored by Peter Daifuku's avatar Peter Daifuku Committed by Bjorn Helgaas
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PCI: tegra: Fix extended configuration space mapping 



The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space.  This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.

Tested-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarPeter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 0d20d621

drivers/pci/host/pci-tegra.c

+1 −1
Original line number Diff line number Diff line
@@ -383,7 +383,7 @@ static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, 
	for (i = 0; i < 16; i++) {

		unsigned long virt = (unsigned long)bus->area->addr +

				     i * SZ_64K;

		phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K;

		phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;



		err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);

		if (err < 0) {