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Commit 8d231c11 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (33 commits)
  [MIPS] Add missing backslashes to macro definitions.
  [MIPS] Death list of board support to be removed after 2.6.18.
  [MIPS] Remove BSD and Sys V compat data types.
  [MIPS] ioc3.h: Uses u8, so include <linux/types.h>.
  [MIPS] 74K: Assume it will also have an AR bit in config7
  [MIPS] Treat CPUs with AR bit as physically indexed.
  [MIPS] Oprofile: Support VSMP on 34K.
  [MIPS] MIPS32/MIPS64 S-cache fix and cleanup
  [MIPS] excite: PCI makefile needs to use += if it wants a chance to work.
  [MIPS] excite: plat_setup -> plat_mem_setup.
  [MIPS] au1xxx: export dbdma functions
  [MIPS] au1xxx: dbdma, no sleeping under spin_lock
  [MIPS] au1xxx: fix PSC_SMBTXRX_RSR.
  [MIPS] Early printk for IP27.
  [MIPS] Fix handling of 0 length I & D caches.
  [MIPS] Typo fixes.
  [MIPS] MIPS32/MIPS64 secondary cache management
  [MIPS] Fix FIXADDR_TOP for TX39/TX49.
  [MIPS] Remove first timer interrupt setup in wrppmc_timer_setup()
  [MIPS] Fix configuration of R2 CPU features and multithreading.
  ...
parents 1f1332f7 8db089c6

Documentation/feature-removal-schedule.txt

+44 −10
Original line number Diff line number Diff line
@@ -132,16 +132,6 @@ Who: NeilBrown <neilb@suse.de> 


---------------------------



What:	au1x00_uart driver

When:	January 2006

Why:	The 8250 serial driver now has the ability to deal with the differences

	between the standard 8250 family of UARTs and their slightly strange

	brother on Alchemy SOCs.  The loss of features is not considered an

	issue.

Who:	Ralf Baechle <ralf@linux-mips.org>



---------------------------



What:   eepro100 network driver

When:   January 2007

Why:    replaced by the e100 driver
@@ -234,3 +224,47 @@ Why: The interface no longer has any callers left in the kernel. It 
Who:	Nick Piggin <npiggin@suse.de>



---------------------------



What:	Support for the MIPS EV96100 evaluation board

When:	September 2006

Why:	Does no longer build since at least November 15, 2003, apparently

	no userbase left.

Who:	Ralf Baechle <ralf@linux-mips.org>



---------------------------



What:	Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board

When:	September 2006

Why:	Does no longer build since quite some time, and was never popular,

	due to the platform being replaced by successor models.  Apparently

	no user base left.  It also is one of the last users of

	WANT_PAGE_VIRTUAL.

Who:	Ralf Baechle <ralf@linux-mips.org>



---------------------------



What:	Support for the Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G

When:	September 2006

Why:	Some do no longer build and apparently there is no user base left

	for these platforms.

Who:	Ralf Baechle <ralf@linux-mips.org>



---------------------------



What:	Support for MIPS Technologies' Altas and SEAD evaluation board

When:	September 2006

Why:	Some do no longer build and apparently there is no user base left

	for these platforms.  Hardware out of production since several years.

Who:	Ralf Baechle <ralf@linux-mips.org>



---------------------------



What:	Support for the IT8172-based platforms, ITE 8172G and Globespan IVR

When:	September 2006

Why:	Code does no longer build since at least 2.6.0,  apparently there is

	no user base left for these platforms.  Hardware out of production

	since several years and hardly a trace of the manufacturer left on

	the net.

Who:	Ralf Baechle <ralf@linux-mips.org>



---------------------------

arch/mips/Kconfig

+64 −32
Original line number Diff line number Diff line
@@ -308,6 +308,7 @@ config MIPS_ATLAS 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL

	help

	  This enables support for the MIPS Technologies Atlas evaluation

	  board.
@@ -324,6 +325,7 @@ config MIPS_MALTA 
	select I8259

	select MIPS_BOARDS_GEN

	select MIPS_BONITO64

	select MIPS_CPU_SCACHE

	select MIPS_GT64120

	select MIPS_MSC

	select SWAP_IO_SPACE
@@ -336,6 +338,7 @@ config MIPS_MALTA 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_MULTITHREADING

	help

	  This enables support for the MIPS Technologies Malta evaluation

	  board.
@@ -358,7 +361,7 @@ config MIPS_SEAD 
	  board.



config WR_PPMC

	bool "Support for Wind River PPMC board"

	bool "Wind River PPMC board"

	select IRQ_CPU

	select BOOT_ELF32

	select DMA_NONCOHERENT
@@ -536,6 +539,7 @@ config PMC_YOSEMITE 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_SUPPORTS_SMP

	help

	  Yosemite is an evaluation board for the RM9000x2 processor

	  manufactured by PMC-Sierra.
@@ -590,6 +594,7 @@ config SGI_IP22 
	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_SMP

	help

	  This are the SGI Indy, Challenge S and Indigo2, as well as certain

	  OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -601,6 +606,7 @@ config SGI_IP27 
	select ARC64

	select BOOT_ELF64

	select DMA_IP27

	select EARLY_PRINTK

	select HW_HAS_PCI

	select PCI_DOMAINS

	select SYS_HAS_CPU_R10000
@@ -1249,7 +1255,7 @@ config CPU_R6000 
	select CPU_SUPPORTS_32BIT_KERNEL

	help

	  MIPS Technologies R6000 and R6000A series processors.  Note these

	  processors are extremly rare and the support for them is incomplete.

	  processors are extremely rare and the support for them is incomplete.



config CPU_NEVADA

	bool "RM52xx"
@@ -1381,7 +1387,7 @@ config CPU_MIPS64 
	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2



#

# These two indicate the revision of the architecture, either 32 bot 64 bit.

# These two indicate the revision of the architecture, either Release 1 or Release 2

#

config CPU_MIPSR1

	bool
@@ -1474,6 +1480,13 @@ config IP22_CPU_SCACHE 
	bool

	select BOARD_SCACHE



#

# Support for a MIPS32 / MIPS64 style S-caches

#

config MIPS_CPU_SCACHE

	bool

	select BOARD_SCACHE



config R5000_CPU_SCACHE

	bool

	select BOARD_SCACHE
@@ -1493,32 +1506,57 @@ config SIBYTE_DMA_PAGEOPS 
config CPU_HAS_PREFETCH

	bool



config MIPS_MT

	bool "Enable MIPS MT"



choice

	prompt "MIPS MT options"

	depends on MIPS_MT



config MIPS_MT_DISABLED

	bool "Disable multithreading support."

	help

	  Use this option if your workload can't take advantage of

	  MIPS hardware multithreading support.  On systems that don't have

	  the option of an MT-enabled processor this option will be the only

	  option in this menu.



config MIPS_MT_SMTC

	bool "SMTC: Use all TCs on all VPEs for SMP"

	depends on CPU_MIPS32_R2

	#depends on CPU_MIPS64_R2		# once there is hardware ...

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_SRS

	select MIPS_MT

	select SMP

	help

	  This is a kernel model which is known a SMTC or lately has been

	  marketesed into SMVP.



config MIPS_MT_SMP

	bool "Use 1 TC on each available VPE for SMP"

	depends on SYS_SUPPORTS_MULTITHREADING

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_SRS

	select MIPS_MT

	select SMP

	help

	  This is a kernel model which is also known a VSMP or lately

	  has been marketesed into SMVP.



config MIPS_VPE_LOADER

	bool "VPE loader support."

	depends on MIPS_MT

	depends on SYS_SUPPORTS_MULTITHREADING

	select MIPS_MT

	help

	  Includes a loader for loading an elf relocatable object

	  onto another VPE and running it.



endchoice



config MIPS_MT

	bool



config SYS_SUPPORTS_MULTITHREADING

	bool



config MIPS_MT_FPAFF

	bool "Dynamic FPU affinity for FP-intensive threads"

	depends on MIPS_MT
@@ -1575,32 +1613,23 @@ config CPU_HAS_LLSC 
config CPU_HAS_WB

	bool



#

# Vectored interrupt mode is an R2 feature

#

config CPU_MIPSR2_IRQ_VI

	bool "Vectored interrupt mode"

	depends on CPU_MIPSR2

	help

	   Vectored interrupt mode allowing faster dispatching of interrupts.

	   The board support code needs to be written to take advantage of this

	   mode.  Compatibility code is included to allow the kernel to run on

	   a CPU that does not support vectored interrupts.  It's safe to

	   say Y here.

	bool



#

# Extended interrupt mode is an R2 feature

#

config CPU_MIPSR2_IRQ_EI

	bool "External interrupt controller mode"

	depends on CPU_MIPSR2

	help

	   Extended interrupt mode takes advantage of an external interrupt

	   controller to allow fast dispatching from many possible interrupt

	   sources. Say N unless you know that external interrupt support is

	   required.

	bool



#

# Shadow registers are an R2 feature

#

config CPU_MIPSR2_SRS

	bool "Make shadow set registers available for interrupt handlers"

	depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI

	help

	   Allow the kernel to use shadow register sets for fast interrupts.

	   Interrupt handlers must be specially written to use shadow sets.

	   Say N unless you know that shadow register set upport is needed.

	bool



config CPU_HAS_SYNC

	bool
@@ -1681,8 +1710,8 @@ source "mm/Kconfig" 


config SMP

	bool "Multi-Processing support"

	depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC

	---help---

	depends on SYS_SUPPORTS_SMP

	help

	  This enables support for systems with more than one CPU. If you have

	  a system with only one CPU, like most personal computers, say N. If

	  you have a system with more than one CPU, say Y.
@@ -1701,6 +1730,9 @@ config SMP 


	  If you don't know what to do here, say N.



config SYS_SUPPORTS_SMP

	bool



config NR_CPUS

	int "Maximum number of CPUs (2-64)"

	range 2 64

arch/mips/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -374,6 +374,7 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ 
cflags-$(CONFIG_PMC_YOSEMITE)	+= -Iinclude/asm-mips/mach-yosemite

load-$(CONFIG_PMC_YOSEMITE)	+= 0xffffffff80100000



#

# Qemu simulating MIPS32 4Kc

#

core-$(CONFIG_QEMU)		+= arch/mips/qemu/

arch/mips/au1000/common/dbdma.c

+5 −1
Original line number Diff line number Diff line
@@ -290,7 +290,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 
				/* If kmalloc fails, it is caught below same

				 * as a channel not available.

				 */

				ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);

				ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);

				chan_tab_ptr[i] = ctp;

				break;

			}
@@ -730,6 +730,8 @@ au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) 
	return rv;

}



EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);



void

au1xxx_dbdma_stop(u32 chanid)

{
@@ -821,6 +823,8 @@ au1xxx_get_dma_residue(u32 chanid) 
	return rv;

}



EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);



void

au1xxx_dbdma_chan_free(u32 chanid)

{

arch/mips/au1000/common/irq.c

+7 −7
Original line number Diff line number Diff line
@@ -585,13 +585,13 @@ void intc1_req1_irqdispatch(struct pt_regs *regs) 
 * au_sleep function in power.c.....maybe I should just pm_register()

 * them instead?

 */

static uint	sleep_intctl_config0[2];

static uint	sleep_intctl_config1[2];

static uint	sleep_intctl_config2[2];

static uint	sleep_intctl_src[2];

static uint	sleep_intctl_assign[2];

static uint	sleep_intctl_wake[2];

static uint	sleep_intctl_mask[2];

static unsigned int	sleep_intctl_config0[2];

static unsigned int	sleep_intctl_config1[2];

static unsigned int	sleep_intctl_config2[2];

static unsigned int	sleep_intctl_src[2];

static unsigned int	sleep_intctl_assign[2];

static unsigned int	sleep_intctl_wake[2];

static unsigned int	sleep_intctl_mask[2];



void

save_au1xxx_intctl(void)