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Commit 8d1806aa authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2014-10-30' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

bunch of DP fixes, and some backlight fix.

* tag 'drm-intel-fixes-2014-10-30' of git://anongit.freedesktop.org/drm-intel:
  drm/i915/dp: only use training pattern 3 on platforms that support it
  drm/i915: Ignore VBT backlight check on Macbook 2, 1
  drm/i915: Fix GMBUSFREQ on vlv/chv
  drm/i915: Ignore long hpds on eDP ports
  drm/i915: Do a dummy DPCD read before the actual read
parents 30aad89a 7809a611

drivers/gpu/drm/i915/intel_display.c

+4 −1
Original line number Diff line number Diff line
@@ -4585,7 +4585,7 @@ static void vlv_update_cdclk(struct drm_device *dev) 
	 * BSpec erroneously claims we should aim for 4MHz, but

	 * in fact 1MHz is the correct frequency.

	 */

	I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);

	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));

}



/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -12885,6 +12885,9 @@ static struct intel_quirk intel_quirks[] = { 
	/* Acer C720 Chromebook (Core i3 4005U) */

	{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },



	/* Apple Macbook 2,1 (Core 2 T7400) */

	{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present },



	/* Toshiba CB35 Chromebook (Celeron 2955U) */

	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },

drivers/gpu/drm/i915/intel_dp.c

+22 −2
Original line number Diff line number Diff line
@@ -2806,6 +2806,13 @@ intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 
	ssize_t ret;

	int i;



	/*

	 * Sometime we just get the same incorrect byte repeated

	 * over the entire buffer. Doing just one throw away read

	 * initially seems to "solve" it.

	 */

	drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);



	for (i = 0; i < 3; i++) {

		ret = drm_dp_dpcd_read(aux, offset, buffer, size);

		if (ret == size)
@@ -3724,9 +3731,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) 
		}

	}



	/* Training Pattern 3 support */

	/* Training Pattern 3 support, both source and sink */

	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&

	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {

	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&

	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {

		intel_dp->use_tps3 = true;

		DRM_DEBUG_KMS("Displayport TPS3 supported\n");

	} else
@@ -4491,6 +4499,18 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)

		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;



	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {

		/*

		 * vdd off can generate a long pulse on eDP which

		 * would require vdd on to handle it, and thus we

		 * would end up in an endless cycle of

		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."

		 */

		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",

			      port_name(intel_dig_port->port));

		return false;

	}



	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",

		      port_name(intel_dig_port->port),

		      long_hpd ? "long" : "short");