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Commit 8cf43455 authored by Agrawal, Nitesh-kumar's avatar Agrawal, Nitesh-kumar Committed by Linus Walleij
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pinctrl/amd: Remove the default de-bounce time 



In the function amd_gpio_irq_enable() and
amd_gpio_direction_input(), remove the code which is setting
the default de-bounce time to 2.75ms.

The driver code shall use the same settings as specified in
BIOS. Any default assignment impacts TouchPad behaviour when
the LevelTrig is set to EDGE FALLING.

Cc: stable@vger.kernel.org
Reviewed-by: default avatar  Ken Xue <Ken.Xue@amd.com>
Signed-off-by: default avatarNitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent b120a3c2

drivers/pinctrl/pinctrl-amd.c

+0 −20
Original line number Original line Diff line number Diff line
@@ -43,17 +43,6 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 




	spin_lock_irqsave(&gpio_dev->lock, flags);

	spin_lock_irqsave(&gpio_dev->lock, flags);

	pin_reg = readl(gpio_dev->base + offset * 4);

	pin_reg = readl(gpio_dev->base + offset * 4);

	/*

	 * Suppose BIOS or Bootloader sets specific debounce for the

	 * GPIO. if not, set debounce to be  2.75ms and remove glitch.

	*/

	if ((pin_reg & DB_TMR_OUT_MASK) == 0) {

		pin_reg |= 0xf;

		pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);

		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;

		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);

	}



	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);

	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);

	writel(pin_reg, gpio_dev->base + offset * 4);

	writel(pin_reg, gpio_dev->base + offset * 4);

	spin_unlock_irqrestore(&gpio_dev->lock, flags);

	spin_unlock_irqrestore(&gpio_dev->lock, flags);
@@ -326,15 +315,6 @@ static void amd_gpio_irq_enable(struct irq_data *d) 




	spin_lock_irqsave(&gpio_dev->lock, flags);

	spin_lock_irqsave(&gpio_dev->lock, flags);

	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);

	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);

	/*

		Suppose BIOS or Bootloader sets specific debounce for the

		GPIO. if not, set debounce to be  2.75ms.

	*/

	if ((pin_reg & DB_TMR_OUT_MASK) == 0) {

		pin_reg |= 0xf;

		pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);

		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);

	}

	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);

	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);

	pin_reg |= BIT(INTERRUPT_MASK_OFF);

	pin_reg |= BIT(INTERRUPT_MASK_OFF);

	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);

	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);