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Commit 8bf7135f authored by Sonic Zhang's avatar Sonic Zhang Committed by Bob Liu
Browse files

blackfin: bf60x: Rename the DDR controller macro 



Rename the DDR controller macro from DDR0 to DMC0 to avoid confustion for
bf60x.

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarBob Liu <lliubbo@gmail.com>
parent 5a84775e

arch/blackfin/kernel/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -856,7 +856,7 @@ static inline int __init get_mem_size(void) 
		ret *= 2;

	return ret;

#elif defined(CONFIG_BF60x)

	u32 ddrctl = bfin_read_DDR0_CFG();

	u32 ddrctl = bfin_read_DMC0_CFG();

	int ret;

	switch (ddrctl & 0xf00) {

	case DEVSZ_64:

arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h

+18 −18
Original line number Diff line number Diff line
@@ -298,24 +298,24 @@ 
#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)



/* DDR2 Memory Control Registers */

#define bfin_read_DDR0_CFG() bfin_read32(DDR0_CFG)

#define bfin_write_DDR0_CFG(val) bfin_write32(DDR0_CFG, val)

#define bfin_read_DDR0_TR0() bfin_read32(DDR0_TR0)

#define bfin_write_DDR0_TR0(val) bfin_write32(DDR0_TR0, val)

#define bfin_read_DDR0_TR1() bfin_read32(DDR0_TR1)

#define bfin_write_DDR0_TR1(val) bfin_write32(DDR0_TR1, val)

#define bfin_read_DDR0_TR2() bfin_read32(DDR0_TR2)

#define bfin_write_DDR0_TR2(val) bfin_write32(DDR0_TR2, val)

#define bfin_read_DDR0_MR() bfin_read32(DDR0_MR)

#define bfin_write_DDR0_MR(val) bfin_write32(DDR0_MR, val)

#define bfin_read_DDR0_EMR1() bfin_read32(DDR0_EMR1)

#define bfin_write_DDR0_EMR1(val) bfin_write32(DDR0_EMR1, val)

#define bfin_read_DDR0_CTL() bfin_read32(DDR0_CTL)

#define bfin_write_DDR0_CTL(val) bfin_write32(DDR0_CTL, val)

#define bfin_read_DDR0_STAT() bfin_read32(DDR0_STAT)

#define bfin_write_DDR0_STAT(val) bfin_write32(DDR0_STAT, val)

#define bfin_read_DDR0_DLLCTL() bfin_read32(DDR0_DLLCTL)

#define bfin_write_DDR0_DLLCTL(val) bfin_write32(DDR0_DLLCTL, val)

#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)

#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)

#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)

#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)

#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)

#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)

#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)

#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)

#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)

#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)

#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)

#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)

#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)

#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)

#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)

#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)

#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)

#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)



/* DDR BankRead and Write Count Registers */

arch/blackfin/mach-bf609/include/mach/defBF60x_base.h

+30 −30
Original line number Diff line number Diff line
@@ -2634,36 +2634,36 @@ 




/* =========================

        DDR Registers

   ========================= */



/* =========================

        DDR0

   ========================= */

#define DDR0_ID                     0xFFC80000         /* DDR0 Identification Register */

#define DDR0_CTL                    0xFFC80004         /* DDR0 Control Register */

#define DDR0_STAT                   0xFFC80008         /* DDR0 Status Register */

#define DDR0_EFFCTL                 0xFFC8000C         /* DDR0 Efficiency Controller */

#define DDR0_PRIO                   0xFFC80010         /* DDR0 Priority ID Register */

#define DDR0_PRIOMSK                0xFFC80014         /* DDR0 Priority ID Mask */

#define DDR0_CFG                    0xFFC80040         /* DDR0 SDRAM Configuration */

#define DDR0_TR0                    0xFFC80044         /* DDR0 Timing Register 0 */

#define DDR0_TR1                    0xFFC80048         /* DDR0 Timing Register 1 */

#define DDR0_TR2                    0xFFC8004C         /* DDR0 Timing Register 2 */

#define DDR0_MSK                    0xFFC8005C         /* DDR0 Mode Register Mask */

#define DDR0_MR                     0xFFC80060         /* DDR0 Mode Shadow register */

#define DDR0_EMR1                   0xFFC80064         /* DDR0 EMR1 Shadow Register */

#define DDR0_EMR2                   0xFFC80068         /* DDR0 EMR2 Shadow Register */

#define DDR0_EMR3                   0xFFC8006C         /* DDR0 EMR3 Shadow Register */

#define DDR0_DLLCTL                 0xFFC80080         /* DDR0 DLL Control Register */

#define DDR0_PADCTL                 0xFFC800C0         /* DDR0 PAD Control Register 0 */



#define DEVSZ_64                0x000         /* DDR External Bank Size = 64Mbit */

#define DEVSZ_128               0x100         /* DDR External Bank Size = 128Mbit */

#define DEVSZ_256               0x200         /* DDR External Bank Size = 256Mbit */

#define DEVSZ_512               0x300         /* DDR External Bank Size = 512Mbit */

#define DEVSZ_1G                0x400         /* DDR External Bank Size = 1Gbit */

#define DEVSZ_2G                0x500         /* DDR External Bank Size = 2Gbit */

        DMC Registers

   ========================= */



/* =========================

        DMC0

   ========================= */

#define DMC0_ID                     0xFFC80000         /* DMC0 Identification Register */

#define DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */

#define DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */

#define DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Controller */

#define DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */

#define DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask */

#define DMC0_CFG                    0xFFC80040         /* DMC0 SDRAM Configuration */

#define DMC0_TR0                    0xFFC80044         /* DMC0 Timing Register 0 */

#define DMC0_TR1                    0xFFC80048         /* DMC0 Timing Register 1 */

#define DMC0_TR2                    0xFFC8004C         /* DMC0 Timing Register 2 */

#define DMC0_MSK                    0xFFC8005C         /* DMC0 Mode Register Mask */

#define DMC0_MR                     0xFFC80060         /* DMC0 Mode Shadow register */

#define DMC0_EMR1                   0xFFC80064         /* DMC0 EMR1 Shadow Register */

#define DMC0_EMR2                   0xFFC80068         /* DMC0 EMR2 Shadow Register */

#define DMC0_EMR3                   0xFFC8006C         /* DMC0 EMR3 Shadow Register */

#define DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */

#define DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register 0 */



#define DEVSZ_64                0x000         /* DMC External Bank Size = 64Mbit */

#define DEVSZ_128               0x100         /* DMC External Bank Size = 128Mbit */

#define DEVSZ_256               0x200         /* DMC External Bank Size = 256Mbit */

#define DEVSZ_512               0x300         /* DMC External Bank Size = 512Mbit */

#define DEVSZ_1G                0x400         /* DMC External Bank Size = 1Gbit */

#define DEVSZ_2G                0x500         /* DMC External Bank Size = 2Gbit */





/* =========================

arch/blackfin/mach-bf609/pm.c

+7 −7
Original line number Diff line number Diff line
@@ -165,11 +165,11 @@ void bf609_ddr_sr(void) 
{

	uint32_t reg;



	reg = bfin_read_DDR0_CTL();

	reg = bfin_read_DMC0_CTL();

	reg |= 0x8;

	bfin_write_DDR0_CTL(reg);

	bfin_write_DMC0_CTL(reg);



	while (!(bfin_read_DDR0_STAT() & 0x8))

	while (!(bfin_read_DMC0_STAT() & 0x8))

		continue;

}
@@ -177,14 +177,14 @@ __attribute__((l1_text)) 
void bf609_ddr_sr_exit(void)

{

	uint32_t reg;

	while (!(bfin_read_DDR0_STAT() & 0x1))

	while (!(bfin_read_DMC0_STAT() & 0x1))

		continue;



	reg = bfin_read_DDR0_CTL();

	reg = bfin_read_DMC0_CTL();

	reg &= ~0x8;

	bfin_write_DDR0_CTL(reg);

	bfin_write_DMC0_CTL(reg);



	while ((bfin_read_DDR0_STAT() & 0x8))

	while ((bfin_read_DMC0_STAT() & 0x8))

		continue;

}