Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8be6a6d0 authored by Javier Martinez Canillas's avatar Javier Martinez Canillas Committed by Kukjin Kim
Browse files

ARM: dts: Set i2c7 clock at 400kHz for exynos based Peach boards 



The downstream ChromeOS 3.8 kernel sets the clock frequency
for the I2C bus 7 at 400kHz. Do the same change in mainline.

Suggested-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent dc0cf1a3

arch/arm/boot/dts/exynos5420-peach-pit.dts

+1 −0
Original line number Diff line number Diff line
@@ -489,6 +489,7 @@ 


&hsi2c_7 {

	status = "okay";

	clock-frequency = <400000>;



	max98090: codec@10 {

		compatible = "maxim,max98090";

arch/arm/boot/dts/exynos5800-peach-pi.dts

+1 −0
Original line number Diff line number Diff line
@@ -487,6 +487,7 @@ 


&hsi2c_7 {

	status = "okay";

	clock-frequency = <400000>;



	max98091: codec@10 {

		compatible = "maxim,max98091";