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Commit 8b8b091b authored by Tony Lindgren's avatar Tony Lindgren Committed by Linus Walleij
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pinctrl: Add one-register-per-pin type device tree based pinctrl driver 



Add one-register-per-pin type device tree based pinctrl driver.

This driver has been tested on omap2+ series of processors,
where there is either an 8 or 16-bit padconf register for each pin.
Support for other similar pinmux controllers can be added.

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 3923040b

Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt

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One-register-per-pin type device tree based pinctrl driver



Required properties:

- compatible : "pinctrl-single"



- reg : offset and length of the register set for the mux registers



- pinctrl-single,register-width : pinmux register access width in bits



- pinctrl-single,function-mask : mask of allowed pinmux function bits

  in the pinmux register



Optional properties:

- pinctrl-single,function-off : function off mode for disabled state if

  available and same for all registers; if not specified, disabling of

  pin functions is ignored



This driver assumes that there is only one register for each pin,

and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt

document in this directory.



The pin configuration nodes for pinctrl-single are specified as pinctrl

register offset and value pairs using pinctrl-single,pins. Only the bits

specified in pinctrl-single,function-mask are updated. For example, setting

a pin for a device could be done with:



	pinctrl-single,pins = <0xdc 0x118>;



Where 0xdc is the offset from the pinctrl register base address for the

device pinctrl register, and 0x118 contains the desired value of the

pinctrl register. See the device example and static board pins example

below for more information.



Example:



/* SoC common file */



/* first controller instance for pins in core domain */

pmx_core: pinmux@4a100040 {

	compatible = "pinctrl-single";

	reg = <0x4a100040 0x0196>;

	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-single,register-width = <16>;

	pinctrl-single,function-mask = <0xffff>;

};



/* second controller instance for pins in wkup domain */

pmx_wkup: pinmux@4a31e040 {

	compatible = "pinctrl-single;

	reg = <0x4a31e040 0x0038>;

	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-single,register-width = <16>;

	pinctrl-single,function-mask = <0xffff>;

};





/* board specific .dts file */



&pmx_core {



	/*

	 * map all board specific static pins enabled by the pinctrl driver

	 * itself during the boot (or just set them up in the bootloader)

	 */

	pinctrl-names = "default";

	pinctrl-0 = <&board_pins>;



	board_pins: pinmux_board_pins {

		pinctrl-single,pins = <

			0x6c 0xf

			0x6e 0xf

			0x70 0xf

			0x72 0xf

		>;

	};



	/* map uart2 pins */

	uart2_pins: pinmux_uart2_pins {

		pinctrl-single,pins = <

			0xd8 0x118

			0xda 0

			0xdc 0x118

			0xde 0

		>;

	};

};



&uart2 {

       pinctrl-names = "default";

       pinctrl-0 = <&uart2_pins>;

};

drivers/pinctrl/Kconfig

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@@ -102,6 +102,14 @@ config PINCTRL_PXA910 
	select PINCTRL_PXA3xx

	select PINCONF



config PINCTRL_SINGLE

	tristate "One-register-per-pin type device tree based pinctrl driver"

	depends on OF

	select PINMUX

	select PINCONF

	help

	  This selects the device tree based generic pinctrl driver.



config PINCTRL_SIRF

	bool "CSR SiRFprimaII pin controller driver"

	depends on ARCH_PRIMA2

drivers/pinctrl/Makefile

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@@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o 
obj-$(CONFIG_PINCTRL_DB8500)	+= pinctrl-nomadik-db8500.o

obj-$(CONFIG_PINCTRL_PXA168)	+= pinctrl-pxa168.o

obj-$(CONFIG_PINCTRL_PXA910)	+= pinctrl-pxa910.o

obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o

obj-$(CONFIG_PINCTRL_SIRF)	+= pinctrl-sirf.o

obj-$(CONFIG_PINCTRL_TEGRA)	+= pinctrl-tegra.o

obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o

drivers/pinctrl/pinctrl-single.c

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File added.

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