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Commit 8b39ab72 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
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Documentation, dt, socfpga: Add Altera Arria10 L2 cache binding 



Add the device tree bindings needed to support the Altera L2 cache on
the Arria10 chip. Since all the peripherals share IRQs, the IRQ fields
are now in the ecc_manager.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-7-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 811fce4f

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

+40 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. 
The ECC Manager counts and corrects single bit errors and counts/handles

double bit errors which are uncorrectable.



Cyclone5 and Arria5 ECC Manager

Required Properties:

- compatible : Should be "altr,socfpga-ecc-manager"

- #address-cells: must be 1
@@ -47,3 +48,42 @@ Example: 
			interrupts = <0 178 1>, <0 179 1>;

		};

	};



Arria10 SoCFPGA ECC Manager

The Arria10 SoC ECC Manager handles the IRQs for each peripheral

in a shared register instead of individual IRQs like the Cyclone5

and Arria5. Therefore the device tree is different as well.



Required Properties:

- compatible : Should be "altr,socfpga-a10-ecc-manager"

- altr,sysgr-syscon : phandle to Arria10 System Manager Block

	containing the ECC manager registers.

- #address-cells: must be 1

- #size-cells: must be 1

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt. Note the rising edge type.

- ranges : standard definition, should translate from local addresses



Subcomponents:



L2 Cache ECC

Required Properties:

- compatible : Should be "altr,socfpga-a10-l2-ecc"

- reg : Address and size for ECC error interrupt clear registers.



Example:



	eccmgr: eccmgr@ffd06000 {

		compatible = "altr,socfpga-a10-ecc-manager";

		altr,sysmgr-syscon = <&sysmgr>;

		#address-cells = <1>;

		#size-cells = <1>;

		interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,

			     <0 0 IRQ_TYPE_LEVEL_HIGH>;

		ranges;



		l2-ecc@ffd06010 {

			compatible = "altr,socfpga-a10-l2-ecc";

			reg = <0xffd06010 0x4>;

		};

	};