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Commit 8ad0df33 authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

clk: rockchip: fix rk3368 cpuclk divider offsets 



Due to a copy-paste error the the rk3368 cpuclk settings were acessing
rk3288-specific register offsets. This never caused problems till now,
as cpu frequency scaling in't used currently at all.

Reported-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 941c4d3f

drivers/clk/rockchip/clk-rk3368.c

+2 −2
Original line number Diff line number Diff line
@@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = { 


#define RK3368_CLKSEL0(_offs, _aclkm)					\

	{								\

		.reg = RK3288_CLKSEL_CON(0 + _offs),			\

		.reg = RK3368_CLKSEL_CON(0 + _offs),			\

		.val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK,	\

				RK3368_DIV_ACLKM_SHIFT),		\

	}

#define RK3368_CLKSEL1(_offs, _atclk, _pdbg)				\

	{								\

		.reg = RK3288_CLKSEL_CON(1 + _offs),			\

		.reg = RK3368_CLKSEL_CON(1 + _offs),			\

		.val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK,	\

				RK3368_DIV_ATCLK_SHIFT) |		\

		       HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK,	\