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Commit 8a9fab22 authored by Divy Le Ray's avatar Divy Le Ray Committed by Jeff Garzik
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cxgb3 - Firmware update



Update FW to 4.1.
Proceed to subsequent HW tuning to improve RDMA perfs..

Signed-off-by: default avatarDivy Le Ray <divy@chelsio.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent cf992af5
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+4 −0
Original line number Diff line number Diff line
@@ -1160,6 +1160,8 @@

#define A_TP_MOD_CHANNEL_WEIGHT 0x434

#define A_TP_MOD_RATE_LIMIT 0x438

#define A_TP_PIO_ADDR 0x440

#define A_TP_PIO_DATA 0x444
@@ -1214,6 +1216,8 @@
#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
			       M_TXDROPCNTCH0RCVD)

#define A_TP_PROXY_FLOW_CNTL 0x4b0

#define A_ULPRX_CTL 0x500

#define S_ROUND_ROBIN    4
+23 −19
Original line number Diff line number Diff line
@@ -921,7 +921,7 @@ static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end)
/*
 *	t3_load_fw - download firmware
 *	@adapter: the adapter
 *	@fw_data: the firrware image to write
 *	@fw_data: the firmware image to write
 *	@size: image size
 *
 *	Write the supplied firmware image to the card's serial flash.
@@ -2362,7 +2362,7 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
		     F_TCPCHECKSUMOFFLOAD | V_IPTTL(64));
	t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
		     F_MTUENABLE | V_WINDOWSCALEMODE(1) |
		     V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1));
		     V_TIMESTAMPSMODE(0) | V_SACKMODE(1) | V_SACKRX(1));
	t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
		     V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
		     V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
@@ -2371,15 +2371,17 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
			 F_IPV6ENABLE | F_NICMODE);
	t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
	t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
	t3_set_reg_field(adap, A_TP_PARA_REG6,
			 adap->params.rev > 0 ? F_ENABLEESND : F_T3A_ENABLEESND,
			 0);
	t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
			 adap->params.rev > 0 ? F_ENABLEESND :
			 F_T3A_ENABLEESND);

	t3_set_reg_field(adap, A_TP_PC_CONFIG,
			 F_ENABLEEPCMDAFULL | F_ENABLEOCSPIFULL,
			 F_TXDEFERENABLE | F_HEARBEATDACK | F_TXCONGESTIONMODE |
			 F_RXCONGESTIONMODE);
			 F_ENABLEEPCMDAFULL,
			 F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
			 F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
	t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
	
	if (adap->params.rev > 0) {
		tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
@@ -2390,9 +2392,10 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
	} else
		t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);

	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0x12121212);
	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0x12121212);
	t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0x1212);
	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
	t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
	t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
}

/* Desired TP timer resolution in usec */
@@ -2468,6 +2471,7 @@ int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh)
		val |= F_RXCOALESCEENABLE;
		if (psh)
			val |= F_RXCOALESCEPSHEN;
		size = min(MAX_RX_COALESCING_LEN, size);
		t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
			     V_MAXRXDATA(MAX_RX_COALESCING_LEN));
	}
@@ -2496,11 +2500,11 @@ static void __devinit init_mtus(unsigned short mtus[])
	 * it can accomodate max size TCP/IP headers when SACK and timestamps
	 * are enabled and still have at least 8 bytes of payload.
	 */
	mtus[0] = 88;
	mtus[1] = 256;
	mtus[2] = 512;
	mtus[3] = 576;
	mtus[4] = 808;
	mtus[1] = 88;
	mtus[1] = 88;
	mtus[2] = 256;
	mtus[3] = 512;
	mtus[4] = 576;
	mtus[5] = 1024;
	mtus[6] = 1280;
	mtus[7] = 1492;
@@ -2802,7 +2806,7 @@ static void init_hw_for_avail_ports(struct adapter *adap, int nports)
		t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
		t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_TPTXPORT0EN |
			     F_PORT0ACTIVE | F_ENFORCEPKT);
		t3_write_reg(adap, A_PM1_TX_CFG, 0xc000c000);
		t3_write_reg(adap, A_PM1_TX_CFG, 0xffffffff);
	} else {
		t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
		t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
@@ -3097,7 +3101,7 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
	else
		t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);

	t3_write_reg(adapter, A_PM1_RX_CFG, 0xf000f000);
	t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
	init_hw_for_avail_ports(adapter, adapter->params.nports);
	t3_sge_init(adapter, &adapter->params.sge);

+1 −1
Original line number Diff line number Diff line
@@ -39,6 +39,6 @@

/* Firmware version */
#define FW_VERSION_MAJOR 4
#define FW_VERSION_MINOR 0
#define FW_VERSION_MINOR 1
#define FW_VERSION_MICRO 0
#endif				/* __CHELSIO_VERSION_H */