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Commit 8a6eac90 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

[TG3]: PCI command adjustment 



This patch changes the way the driver works with the PCI command
register.  It adjusts the access size from dwords to words.  This patch
is done both as a PCI configuration space cleanup and as preparatory
work for PCI error recovery.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9c8a620e

drivers/net/tg3.c

+2 −5
Original line number Diff line number Diff line
@@ -5029,10 +5029,7 @@ static int tg3_poll_fw(struct tg3 *tp) 
/* Save PCI command register before chip reset */

static void tg3_save_pci_state(struct tg3 *tp)

{

	u32 val;



	pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);

	tp->pci_cmd = val;

	pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);

}



/* Restore PCI state after chip reset */
@@ -5055,7 +5052,7 @@ static void tg3_restore_pci_state(struct tg3 *tp) 
		       PCISTATE_ALLOW_APE_SHMEM_WR;

	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);



	pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);

	pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);



	if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {

		pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,

drivers/net/tg3.h

+1 −1
Original line number Diff line number Diff line
@@ -2421,7 +2421,7 @@ struct tg3 { 
#define PHY_REV_BCM5411_X0		0x1 /* Found on Netgear GA302T */



	u32				led_ctrl;

	u32				pci_cmd;

	u16				pci_cmd;



	char				board_part_number[24];

#define TG3_VER_SIZE 32