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Commit 8954672d authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq core updates from Thomas Gleixner:
 "Managerial summary:

  Core code:
   - final removal of IRQF_DISABLED
   - new state save/restore functions for virtualization support
   - wakeup support for stacked irqdomains
   - new function to solve the netpoll synchronization problem

 irqchips:
   - new driver for STi based devices
   - new driver for Vybrid MSCM
   - massive cleanup of the GIC driver by moving the GIC-addons to
     stacked irqdomains
   - the usual pile of fixes and updates to the various chip drivers"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
  irqchip: GICv3: Add support for irq_[get, set]_irqchip_state()
  irqchip: GIC: Add support for irq_[get, set]_irqchip_state()
  genirq: Allow the irqchip state of an IRQ to be save/restored
  genirq: MSI: Fix freeing of unallocated MSI
  irqchip: renesas-irqc: Add wake-up support
  irqchip: armada-370-xp: Allow using wakeup source
  irqchip: mips-gic: Add new functions to start/stop the GIC counter
  irqchip: tegra: Add Tegra210 support
  irqchip: digicolor: Move digicolor_set_gc to init section
  irqchip: renesas-irqc: Add functional clock to bindings
  irqchip: renesas-irqc: Add minimal runtime PM support
  irqchip: renesas-irqc: Add more register documentation
  DT: exynos: update PMU binding
  ARM: exynos4/5: convert pmu wakeup to stacked domains
  irqchip: gic: Don't complain in gic_get_cpumask() if UP system
  ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
  ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
  ARM: shmobile: remove use of gic_arch_extn.irq_set_wake
  irqchip: gic: Add an entry point to set up irqchip flags
  ARM: omap: convert wakeupgen to stacked domains
  ...
parents 3be1b98e b7dccbea

Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt

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+14 −0
Original line number Diff line number Diff line 
Freescale Vybrid Miscellaneous System Control - CPU Configuration



The MSCM IP contains multiple sub modules, this binding describes the first

block of registers which contains CPU configuration information.



Required properties:

- compatible:	"fsl,vf610-mscm-cpucfg", "syscon"

- reg:		the register range of the MSCM CPU configuration registers



Example:

	mscm_cpucfg: cpucfg@40001000 {

		compatible = "fsl,vf610-mscm-cpucfg", "syscon";

		reg = <0x40001000 0x800>;

	}

Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt

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+33 −0
Original line number Diff line number Diff line 
Freescale Vybrid Miscellaneous System Control - Interrupt Router



The MSCM IP contains multiple sub modules, this binding describes the second

block of registers which control the interrupt router. The interrupt router

allows to configure the recipient of each peripheral interrupt. Furthermore

it controls the directed processor interrupts. The module is available in all

Vybrid SoC's but is only really useful in dual core configurations (VF6xx

which comes with a Cortex-A5/Cortex-M4 combination).



Required properties:

- compatible:		"fsl,vf610-mscm-ir"

- reg:			the register range of the MSCM Interrupt Router

- fsl,cpucfg:		The handle to the MSCM CPU configuration node, required

			to get the current CPU ID

- interrupt-controller:	Identifies the node as an interrupt controller

- #interrupt-cells:	Two cells, interrupt number and cells.

			The hardware interrupt number according to interrupt

			assignment of the interrupt router is required.

			Flags get passed only when using GIC as parent. Flags

			encoding as documented by the GIC bindings.

- interrupt-parent:	Should be the phandle for the interrupt controller of

			the CPU the device tree is intended to be used on. This

			is either the node of the GIC or NVIC controller.



Example:

	mscm_ir: interrupt-controller@40001800 {

		compatible = "fsl,vf610-mscm-ir";

		reg = <0x40001800 0x400>;

		fsl,cpucfg = <&mscm_cpucfg>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupt-parent = <&intc>;

	}

Documentation/devicetree/bindings/arm/gic.txt

+0 −6
Original line number Diff line number Diff line
@@ -56,11 +56,6 @@ Optional 
  regions, used when the GIC doesn't have banked registers. The offset is

  cpu-offset * cpu-nr.



- arm,routable-irqs : Total number of gic irq inputs which are not directly

		  connected from the peripherals, but are routed dynamically

		  by a crossbar/multiplexer preceding the GIC. The GIC irq

		  input line is assigned dynamically when the corresponding

		  peripheral's crossbar line is mapped.

Example:



	intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example: 
		#interrupt-cells = <3>;

		#address-cells = <1>;

		interrupt-controller;

		arm,routable-irqs = <160>;

		reg = <0xfff11000 0x1000>,

		      <0xfff10100 0x100>;

	};

Documentation/devicetree/bindings/arm/omap/crossbar.txt

+5 −13
Original line number Diff line number Diff line
@@ -9,7 +9,9 @@ inputs. 
Required properties:

- compatible : Should be "ti,irq-crossbar"

- reg: Base address and the size of the crossbar registers.

- ti,max-irqs: Total number of irqs available at the interrupt controller.

- interrupt-controller: indicates that this block is an interrupt controller.

- interrupt-parent: the interrupt controller this block is connected to.

- ti,max-irqs: Total number of irqs available at the parent interrupt controller.

- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.

- ti,reg-size: Size of a individual register in bytes. Every individual

	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties: 
  when the interrupt controller irq is unused (when not provided, default is 0)



Examples:

		crossbar_mpu: @4a020000 {

		crossbar_mpu: crossbar@4a002a48 {

			compatible = "ti,irq-crossbar";

			reg = <0x4a002a48 0x130>;

			ti,max-irqs = <160>;

			ti,max-crossbar-sources = <400>;

			ti,reg-size = <2>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;

			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;

			ti,irqs-skip = <10 133 139 140>;

		};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details. 


An interrupt consumer on an SoC using crossbar will use:

	interrupts = <GIC_SPI request_number interrupt_level>

When the request number is between 0 to that described by

"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the

request_number is greater than "ti,max-crossbar-sources", then it is mapped as a

quirky hardware mapping direct to GIC.



Example:

	device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example: 
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		...

	};
 


	device_y@0x4a033000 {

		/* Direct mapped GIC SPI 1 used */

		interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;

		...

	};

Documentation/devicetree/bindings/arm/samsung/pmu.txt

+17 −0
Original line number Diff line number Diff line
@@ -29,10 +29,27 @@ Properties: 
 - clocks : list of phandles and specifiers to all input clocks listed in

		clock-names property.



Optional properties:



Some PMUs are capable of behaving as an interrupt controller (mostly

to wake up a suspended PMU). In which case, they can have the

following properties:



- interrupt-controller: indicate that said PMU is an interrupt controller



- #interrupt-cells: must be identical to the that of the parent interrupt

  controller.



- interrupt-parent: a phandle indicating which interrupt controller

  this PMU signals interrupts to.



Example :

pmu_system_controller: system-controller@10040000 {

	compatible = "samsung,exynos5250-pmu", "syscon";

	reg = <0x10040000 0x5000>;

	interrupt-controller;

	#interrupt-cells = <3>;

	interrupt-parent = <&gic>;

	#clock-cells = <1>;

	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",

			"clkout4", "clkout8", "clkout9";