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Commit 88f9eae4 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: programm the VCE fw BAR as well 



Otherwise the VCE firmware needs to be in the first 256MB of VRAM.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1b01fc34

drivers/gpu/drm/radeon/cikd.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -2129,6 +2129,7 @@ 
#define VCE_UENC_REG_CLOCK_GATING	0x207c0

#define VCE_UENC_REG_CLOCK_GATING	0x207c0

#define VCE_SYS_INT_EN			0x21300

#define VCE_SYS_INT_EN			0x21300

#	define VCE_SYS_INT_TRAP_INTERRUPT_EN	(1 << 3)

#	define VCE_SYS_INT_TRAP_INTERRUPT_EN	(1 << 3)

#define VCE_LMI_VCPU_CACHE_40BIT_BAR	0x2145c

#define VCE_LMI_CTRL2			0x21474

#define VCE_LMI_CTRL2			0x21474

#define VCE_LMI_CTRL			0x21498

#define VCE_LMI_CTRL			0x21498

#define VCE_LMI_VM_CTRL			0x214a0

#define VCE_LMI_VM_CTRL			0x214a0

drivers/gpu/drm/radeon/vce_v2_0.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev) 
	WREG32(VCE_LMI_SWAP_CNTL1, 0);

	WREG32(VCE_LMI_SWAP_CNTL1, 0);

	WREG32(VCE_LMI_VM_CTRL, 0);

	WREG32(VCE_LMI_VM_CTRL, 0);





	WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);



	addr &= 0xff;

	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);

	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);

	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);

	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);

	WREG32(VCE_VCPU_CACHE_SIZE0, size);

	WREG32(VCE_VCPU_CACHE_SIZE0, size);