Commit 88c9a65e authored Feb 09, 2012 by Stephane Eranian Committed by Ingo Molnar Mar 05, 2012

perf/x86: Disable LBR support for older Intel Atom processors



The patch adds a restriction for Intel Atom LBR support. Only
steppings 10 (PineView) and more recent are supported. Older models
do not have a functional LBR. Their LBR does not freeze on PMU
interrupt which makes LBR unusable in the context of perf_events.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1328826068-11713-7-git-send-email-eranian@google.com


Signed-off-by: Ingo Molnar <mingo@elte.hu>

parent c5cc2cd9

arch/x86/kernel/cpu/perf_event_intel_lbr.c

+10 −0

Original line number	Original line	Diff line number	Diff line
	@@ -315,6 +315,16 @@ void intel_pmu_lbr_init_snb(void)
	/* atom */		/* atom */
	void intel_pmu_lbr_init_atom(void)		void intel_pmu_lbr_init_atom(void)
	{		{
			/*
			* only models starting at stepping 10 seems
			* to have an operational LBR which can freeze
			* on PMU interrupt
			*/
			if (boot_cpu_data.x86_mask < 10) {
			pr_cont("LBR disabled due to erratum");
			return;
			}

	x86_pmu.lbr_nr = 8;		x86_pmu.lbr_nr = 8;
	x86_pmu.lbr_tos = MSR_LBR_TOS;		x86_pmu.lbr_tos = MSR_LBR_TOS;
	x86_pmu.lbr_from = MSR_LBR_CORE_FROM;		x86_pmu.lbr_from = MSR_LBR_CORE_FROM;