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Commit 87d31345 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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Merge commit 'gcl/next' into next

parents e98efaf3 d24720a4

Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt

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MPC5121 PSC Device Tree Bindings



PSC in UART mode

----------------



For PSC in UART mode the needed PSC serial devices

are specified by fsl,mpc5121-psc-uart nodes in the

fsl,mpc5121-immr SoC node. Additionally the PSC FIFO

Controller node fsl,mpc5121-psc-fifo is requered there:



fsl,mpc5121-psc-uart nodes

--------------------------



Required properties :

 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"

 - cell-index : Index of the PSC in hardware

 - reg : Offset and length of the register set for the PSC device

 - interrupts : <a b> where a is the interrupt number of the

   PSC FIFO Controller and b is a field that represents an

   encoding of the sense and level information for the interrupt.

 - interrupt-parent : the phandle for the interrupt controller that

   services interrupts for this device.



Recommended properties :

 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)

 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)





fsl,mpc5121-psc-fifo node

-------------------------



Required properties :

 - compatible : Should be "fsl,mpc5121-psc-fifo"

 - reg : Offset and length of the register set for the PSC

         FIFO Controller

 - interrupts : <a b> where a is the interrupt number of the

   PSC FIFO Controller and b is a field that represents an

   encoding of the sense and level information for the interrupt.

 - interrupt-parent : the phandle for the interrupt controller that

   services interrupts for this device.





Example for a board using PSC0 and PSC1 devices in serial mode:



serial@11000 {

	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";

	cell-index = <0>;

	reg = <0x11000 0x100>;

	interrupts = <40 0x8>;

	interrupt-parent = < &ipic >;

	fsl,rx-fifo-size = <16>;

	fsl,tx-fifo-size = <16>;

};



serial@11100 {

	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";

	cell-index = <1>;

	reg = <0x11100 0x100>;

	interrupts = <40 0x8>;

	interrupt-parent = < &ipic >;

	fsl,rx-fifo-size = <16>;

	fsl,tx-fifo-size = <16>;

};



pscfifo@11f00 {

	compatible = "fsl,mpc5121-psc-fifo";

	reg = <0x11f00 0x100>;

	interrupts = <40 0x8>;

	interrupt-parent = < &ipic >;

};

Documentation/powerpc/dts-bindings/fsl/spi.txt

+7 −0
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@@ -13,6 +13,11 @@ Required properties: 
- interrupt-parent : the phandle for the interrupt controller that

  services interrupts for this device.



Optional properties:

- gpios : specifies the gpio pins to be used for chipselects.

  The gpios will be referred to as reg = <index> in the SPI child nodes.

  If unspecified, a single SPI device without a chip select can be used.



Example:

	spi@4c0 {

		cell-index = <0>;
@@ -21,4 +26,6 @@ Example: 
		interrupts = <82 0>;

		interrupt-parent = <700>;

		mode = "cpu";

		gpios = <&gpio 18 1	// device reg=<0>

			 &gpio 19 1>;	// device reg=<1>

	};

arch/powerpc/boot/dts/mpc5121ads.dts

+33 −22
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@@ -62,17 +62,12 @@ 
		interrupt-parent = < &ipic >;

		#address-cells = <1>;

		#size-cells = <1>;

		bank-width = <1>;

		// ADS has two Hynix 512MB Nand flash chips in a single

		// stacked package.

		chips = <2>;

		nand0@0 {

			label = "nand0";

			reg = <0x00000000 0x02000000>; 	// first 32 MB of chip 0

		};

		nand1@20000000 {

			label = "nand1";

			reg = <0x20000000 0x02000000>; 	// first 32 MB of chip 1

		nand@0 {

			label = "nand";

			reg = <0x00000000 0x40000000>;	// 512MB + 512MB

		};

	};
@@ -166,6 +161,11 @@ 
			interrupt-parent = < &ipic >;

		};



		reset@e00 {	// Reset module

			compatible = "fsl,mpc5121-reset";

			reg = <0xe00 0x100>;

		};



		clock@f00 {	// Clock control

			compatible = "fsl,mpc5121-clock";

			reg = <0xf00 0x100>;
@@ -185,17 +185,15 @@ 
			interrupt-parent = < &ipic >;

		};



		mscan@1300 {

		can@1300 {

			compatible = "fsl,mpc5121-mscan";

			cell-index = <0>;

			interrupts = <12 0x8>;

			interrupt-parent = < &ipic >;

			reg = <0x1300 0x80>;

		};



		mscan@1380 {

		can@1380 {

			compatible = "fsl,mpc5121-mscan";

			cell-index = <1>;

			interrupts = <13 0x8>;

			interrupt-parent = < &ipic >;

			reg = <0x1380 0x80>;
@@ -205,17 +203,31 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			cell-index = <0>;

			reg = <0x1700 0x20>;

			interrupts = <9 0x8>;

			interrupt-parent = < &ipic >;

			fsl,preserve-clocking;



			hwmon@4a {

				compatible = "adi,ad7414";

				reg = <0x4a>;

			};



			eeprom@50 {

				compatible = "at,24c32";

				reg = <0x50>;

			};



			rtc@68 {

				compatible = "stm,m41t62";

				reg = <0x68>;

			};

		};



		i2c@1720 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			cell-index = <1>;

			reg = <0x1720 0x20>;

			interrupts = <10 0x8>;

			interrupt-parent = < &ipic >;
@@ -225,7 +237,6 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			cell-index = <2>;

			reg = <0x1740 0x20>;

			interrupts = <11 0x8>;

			interrupt-parent = < &ipic >;
@@ -244,7 +255,7 @@ 
		};



		display@2100 {

			compatible = "fsl,mpc5121-diu", "fsl-diu";

			compatible = "fsl,mpc5121-diu";

			reg = <0x2100 0x100>;

			interrupts = <64 0x8>;

			interrupt-parent = < &ipic >;
@@ -277,7 +288,7 @@ 


		// USB1 using external ULPI PHY

		//usb@3000 {

		//	compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";

		//	compatible = "fsl,mpc5121-usb2-dr";

		//	reg = <0x3000 0x1000>;

		//	#address-cells = <1>;

		//	#size-cells = <0>;
@@ -285,12 +296,11 @@ 
		//	interrupts = <43 0x8>;

		//	dr_mode = "otg";

		//	phy_type = "ulpi";

		//	port1;

		//};



		// USB0 using internal UTMI PHY

		usb@4000 {

			compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";

			compatible = "fsl,mpc5121-usb2-dr";

			reg = <0x4000 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -298,7 +308,8 @@ 
			interrupts = <44 0x8>;

			dr_mode = "otg";

			phy_type = "utmi_wide";

			port0;

			fsl,invert-drvvbus;

			fsl,invert-pwr-fault;

		};



		// IO control
@@ -365,7 +376,7 @@ 
		};



		dma@14000 {

			compatible = "fsl,mpc5121-dma2";

			compatible = "fsl,mpc5121-dma";

			reg = <0x14000 0x1800>;

			interrupts = <65 0x8>;

			interrupt-parent = < &ipic >;

arch/powerpc/configs/mpc512x_defconfig

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arch/powerpc/include/asm/mpc5121.h

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/*

 * MPC5121 Prototypes and definitions

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.

 */



#ifndef __ASM_POWERPC_MPC5121_H__

#define __ASM_POWERPC_MPC5121_H__



/* MPC512x Reset module registers */

struct mpc512x_reset_module {

	u32	rcwlr;	/* Reset Configuration Word Low Register */

	u32	rcwhr;	/* Reset Configuration Word High Register */

	u32	reserved1;

	u32	reserved2;

	u32	rsr;	/* Reset Status Register */

	u32	rmr;	/* Reset Mode Register */

	u32	rpr;	/* Reset Protection Register */

	u32	rcr;	/* Reset Control Register */

	u32	rcer;	/* Reset Control Enable Register */

};



#endif /* __ASM_POWERPC_MPC5121_H__ */