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Commit 87d0f939 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2016-02-04' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

misc i915 fixes.

* tag 'drm-intel-fixes-2016-02-04' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: refine qemu south bridge detection
  drm/i915: Remove select to deleted STOP_MACHINE from Kconfig
  drm/i915: Fix NULL plane->fb oops on SKL
  drm/i915: Don't reject primary plane windowing with color keying enabled on SKL+
  drm/i915/dp: fall back to 18 bpp when sink capability is unknown
  drm/i915: Make sure DC writes are coherent on flush.
parents 36f90b0a f2e30510

drivers/gpu/drm/i915/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ config DRM_I915 
	# the shmem_readpage() which depends upon tmpfs

	select SHMEM

	select TMPFS

	select STOP_MACHINE

	select DRM_KMS_HELPER

	select DRM_PANEL

	select DRM_MIPI_DSI

drivers/gpu/drm/i915/i915_drv.c

+3 −1
Original line number Diff line number Diff line
@@ -501,7 +501,9 @@ void intel_detect_pch(struct drm_device *dev) 
				WARN_ON(!IS_SKYLAKE(dev) &&

					!IS_KABYLAKE(dev));

			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||

				   (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) {

				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&

				    pch->subsystem_vendor == 0x1af4 &&

				    pch->subsystem_device == 0x1100)) {

				dev_priv->pch_type = intel_virt_detect_pch(dev);

			} else

				continue;

drivers/gpu/drm/i915/intel_display.c

+22 −11
Original line number Diff line number Diff line
@@ -2946,7 +2946,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane, 
	struct i915_vma *vma;

	u64 offset;



	intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,

	intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,

				intel_plane->base.state);



	vma = i915_gem_obj_to_ggtt_view(obj, &view);
@@ -12075,11 +12075,21 @@ connected_sink_compute_bpp(struct intel_connector *connector, 
		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;

	}



	/* Clamp bpp to 8 on screens without EDID 1.4 */

	if (connector->base.display_info.bpc == 0 && bpp > 24) {

		DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",

			      bpp);

		pipe_config->pipe_bpp = 24;

	/* Clamp bpp to default limit on screens without EDID 1.4 */

	if (connector->base.display_info.bpc == 0) {

		int type = connector->base.connector_type;

		int clamp_bpp = 24;



		/* Fall back to 18 bpp when DP sink capability is unknown. */

		if (type == DRM_MODE_CONNECTOR_DisplayPort ||

		    type == DRM_MODE_CONNECTOR_eDP)

			clamp_bpp = 18;



		if (bpp > clamp_bpp) {

			DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",

				      bpp, clamp_bpp);

			pipe_config->pipe_bpp = clamp_bpp;

		}

	}

}
@@ -13883,11 +13893,12 @@ intel_check_primary_plane(struct drm_plane *plane, 
	int max_scale = DRM_PLANE_HELPER_NO_SCALING;

	bool can_position = false;



	if (INTEL_INFO(plane->dev)->gen >= 9) {

		/* use scaler when colorkey is not required */

	if (INTEL_INFO(plane->dev)->gen >= 9 &&

	    state->ckey.flags == I915_SET_COLORKEY_NONE) {

		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {

			min_scale = 1;

			max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);

		}

		can_position = true;

	}

drivers/gpu/drm/i915/intel_lrc.c

+1 −0
Original line number Diff line number Diff line
@@ -1707,6 +1707,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, 
	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −0
Original line number Diff line number Diff line
@@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, 
	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}

	if (invalidate_domains) {
@@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req, 
	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}

	if (invalidate_domains) {