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Commit 87c779ba authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:
 "Main features this time are:

   - BAM v1.3.0 support form qcom bam dma
   - support for Allwinner sun8i dma
   - atmels eXtended DMA Controller driver
   - chancnt cleanup by Maxime
   - fixes spread over drivers"

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (56 commits)
  dmaenegine: Delete a check before free_percpu()
  dmaengine: ioatdma: fix dma mapping errors
  dma: cppi41: add a delay while setting the TD bit
  dma: cppi41: wait longer for the HW to return the descriptor
  dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model
  dmaengine: fsl-edma: fix calculation of remaining bytes
  drivers/dma/pch_dma: declare pch_dma_id_table as static
  dmaengine: ste_dma40: fix error return code
  dma: imx-sdma: clarify about firmware not found error
  Documentation: devicetree: Fix Xilinx VDMA specification
  dmaengine: pl330: update author info
  dmaengine: clarify the issue_pending expectations
  dmaengine: at_xdmac: Add DMA_PRIVATE
  ARM: dts: at_xdmac: fix bad value of dma-cells in documentation
  dmaengine: at_xdmac: fix missing spin_unlock
  dmaengine: at_xdmac: fix a bug in transfer residue computation
  dmaengine: at_xdmac: fix software lockup at_xdmac_tx_status()
  dmaengine: at_xdmac: remove chancnt affectation
  dmaengine: at_xdmac: prefer usage of readl/writel_relaxed
  dmaengine: xdmac: fix print warning on dma_addr_t variable
  ...
parents eea0cf3f a9507ca3

Documentation/devicetree/bindings/dma/atmel-xdma.txt

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* Atmel Extensible Direct Memory Access Controller (XDMAC)



* XDMA Controller

Required properties:

- compatible: Should be "atmel,<chip>-dma".

  <chip> compatible description:

  - sama5d4: first SoC adding the XDMAC

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <1>, used to represent the number of integer cells in

the dmas property of client devices.

  - The 1st cell specifies the channel configuration register:

    - bit 13: SIF, source interface identifier, used to get the memory

    interface identifier,

    - bit 14: DIF, destination interface identifier, used to get the peripheral

    interface identifier,

    - bit 30-24: PERID, peripheral identifier.



Example:



dma1: dma-controller@f0004000 {

	compatible = "atmel,sama5d4-dma";

	reg = <0xf0004000 0x200>;

	interrupts = <50 4 0>;

	#dma-cells = <1>;

};





* DMA clients

DMA clients connected to the Atmel XDMA controller must use the format

described in the dma.txt file, using a one-cell specifier for each channel.

The two cells in order are:

1. A phandle pointing to the DMA controller.

2. Channel configuration register. Configurable fields are:

    - bit 13: SIF, source interface identifier, used to get the memory

    interface identifier,

    - bit 14: DIF, destination interface identifier, used to get the peripheral

    interface identifier,

  - bit 30-24: PERID, peripheral identifier.



Example:



i2c2: i2c@f8024000 {

	compatible = "atmel,at91sam9x5-i2c";

	reg = <0xf8024000 0x4000>;

	interrupts = <34 4 6>;

	dmas = <&dma1

		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)

		 | AT91_XDMAC_DT_PERID(6))>,

	       <&dma1

		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)

		| AT91_XDMAC_DT_PERID(7))>;

	dma-names = "tx", "rx";

};

Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt

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@@ -48,6 +48,7 @@ The full ID of peripheral types can be found below. 
	21	ESAI

	22	SSI Dual FIFO	(needs firmware ver >= 2)

	23	Shared ASRC

	24	SAI



The third cell specifies the transfer priority as below.

Documentation/devicetree/bindings/dma/qcom_bam_dma.txt

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QCOM BAM DMA controller



Required properties:

- compatible: must contain "qcom,bam-v1.4.0" for MSM8974

- compatible: must be one of the following:

 * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084

 * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960

- reg: Address range for DMA registers

- interrupts: Should contain the one interrupt shared by all channels

- #dma-cells: must be <1>, the cell in the dmas property of the client device

Documentation/devicetree/bindings/dma/sun6i-dma.txt

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@@ -4,7 +4,7 @@ This driver follows the generic DMA bindings defined in dma.txt. 


Required properties:



- compatible:	Must be "allwinner,sun6i-a31-dma"

- compatible:	Must be "allwinner,sun6i-a31-dma" or "allwinner,sun8i-a23-dma"

- reg:		Should contain the registers base address and length

- interrupts:	Should contain a reference to the interrupt used by this device

- clocks:	Should contain a reference to the parent AHB clock