Merge tag 'devicetree-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

DT bindings for the R-Mobile/R-Car interrupt controller

DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller

Required properties:

- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.

  Examples with soctypes are:

    - "renesas,irqc-r8a73a4" (R-Mobile APE6)

    - "renesas,irqc-r8a7743" (RZ/G1M)

    - "renesas,irqc-r8a7745" (RZ/G1E)

    - "renesas,irqc-r8a7790" (R-Car H2)

    - "renesas,irqc-r8a7791" (R-Car M2-W)

    - "renesas,irqc-r8a7792" (R-Car V2H)

- interrupt-parent :  The parent interrupt controller.

Optional properties:

- regulators : The regulators of max77693 have to be instantiated under subnod

- regulators : The regulators of max77693 have to be instantiated under subnode

  named "regulators" using the following format.

	regulators {

		regualtor-compatible = ESAFEOUT1/ESAFEOUT2/CHARGER

		standard regulator constratints[*].

		regulator-compatible = ESAFEOUT1/ESAFEOUT2/CHARGER

		standard regulator constraints[*].

	};

	[*] refer Documentation/devicetree/bindings/regulator/regulator.txt

- haptic : The MAX77693 haptic device utilises a PWM controlled motor to provide

  users with tactile feedback. PWM period and duty-cycle are varied in

  order to provide the approprite level of feedback.

  order to provide the appropriate level of feedback.

 Required properties:

	- compatible : Must be "maxim,max77693-hpatic"

	- compatible : Must be "maxim,max77693-haptic"

	- haptic-supply : power supply for the haptic motor

	[*] refer Documentation/devicetree/bindings/regulator/regulator.txt

	- pwms : phandle to the physical PWM(Pulse Width Modulation) device.

	 PWM properties should be named "pwms". And number of cell is different

	 for each pwm device.

	 To get more informations, please refer to documentaion.

	 To get more information, please refer to documentation.

	[*] refer Documentation/devicetree/bindings/pwm/pwm.txt

- charger : Node configuring the charger driver.

* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)

This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)

IP block. The IP supports multiple options for bus type, clocking and reset

structure, and feature list. Consequently, a number of properties and list

entries in properties are marked as optional, or only required in specific HW

configurations.

Required properties:

- compatible: Should be "snps,dwc-qos-ethernet-4.10"

- compatible: One of:

  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"

    Represents the IP core when integrated into the Axis ARTPEC-6 SoC.

  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"

    Represents the IP core when integrated into the NVIDIA Tegra186 SoC.

  - "snps,dwc-qos-ethernet-4.10"

    This combination is deprecated. It should be treated as equivalent to

    "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be

    compatible with earlier revisions of this binding.

- reg: Address and length of the register set for the device

- clocks: Phandles to the reference clock and the bus clock

- clock-names: Should be "phy_ref_clk" for the reference clock and "apb_pclk"

  for the bus clock.

- clocks: Phandle and clock specifiers for each entry in clock-names, in the

  same order. See ../clock/clock-bindings.txt.

- clock-names: May contain any/all of the following depending on the IP

  configuration, in any order:

  - "tx"

    The EQOS transmit path clock. The HW signal name is clk_tx_i.

    In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX

    path. In other configurations, other clocks (such as tx_125, rmii) may

    drive the PHY TX path.

  - "rx"

    The EQOS receive path clock. The HW signal name is clk_rx_i.

    In some configurations (e.g. GMII/RGMII), this clock is derived from the

    PHY's RX clock output. In other configurations, other clocks (such as

    rx_125, rmii) may drive the EQOS RX path.

    In cases where the PHY clock is directly fed into the EQOS receive path

    without intervening logic, the DT need not represent this clock, since it

    is assumed to be fully under the control of the PHY device/driver. In

    cases where SoC integration adds additional logic to this path, such as a

    SW-controlled clock gate, this clock should be represented in DT.

  - "slave_bus"

    The CPU/slave-bus (CSR) interface clock. This applies to any bus type;

    APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other

    buses).

  - "master_bus"

    The master bus interface clock. Only required in configurations that use a

    separate clock for the master and slave bus interfaces. The HW signal name

    is hclk_i (AHB) or aclk_i (AXI).

  - "ptp_ref"

    The PTP reference clock. The HW signal name is clk_ptp_ref_i.

  - "phy_ref_clk"

    This clock is deprecated and should not be used by new compatible values.

    It is equivalent to "tx".

  - "apb_pclk"

    This clock is deprecated and should not be used by new compatible values.

    It is equivalent to "slave_bus".

  Note: Support for additional IP configurations may require adding the

  following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,

  clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.

  Configurations exist where multiple similar clocks are used at once, e.g. all

  of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to

  extend the binding with a separate clock-names entry for each of those RX

  clocks, rather than repurposing the existing "rx" clock-names entry as a

  generic/logical clock in a similar fashion to "master_bus" and "slave_bus".

  This will allow easy support for configurations that support multiple PHY

  interfaces using a mux, and hence need to have explicit control over

  specific RX clocks.

  The following compatible values require the following set of clocks:

  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":

    - "slave_bus"

    - "master_bus"

    - "rx"

    - "tx"

    - "ptp_ref"

  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":

    - "slave_bus"

    - "master_bus"

    - "tx"

    - "ptp_ref"

  - "snps,dwc-qos-ethernet-4.10" (deprecated):

    - "phy_ref_clk"

    - "apb_clk"

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the core's combined interrupt signal

- phy-mode: See ethernet.txt file in the same directory

- resets: Phandle and reset specifiers for each entry in reset-names, in the

  same order. See ../reset/reset.txt.

- reset-names: May contain any/all of the following depending on the IP

  configuration, in any order:

  - "eqos". The reset to the entire module. The HW signal name is hreset_n

    (AHB) or aresetn_i (AXI).

  The following compatible values require the following set of resets:

  (the reset properties may be omitted if empty)

  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":

    - "eqos".

  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":

    - None.

  - "snps,dwc-qos-ethernet-4.10" (deprecated):

    - None.

Optional properties:

- dma-coherent: Present if dma operations are coherent

- mac-address: See ethernet.txt in the same directory

- local-mac-address: See ethernet.txt in the same directory

- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.

  See ../gpio/gpio.txt.

- snps,en-lpi: If present it enables use of the AXI low-power interface

- snps,write-requests: Number of write requests that the AXI port can issue.

  It depends on the SoC configuration.

	reg = <0x40010000 0x4000>;

	phy-handle = <&phy2>;

	phy-mode = "gmii";

	phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;

	snps,en-tx-lpi-clockgating;

	snps,en-lpi;

Espressif ESP8089 wireless SDIO devices

This node provides properties for controlling the ESP8089 wireless device.

The node is expected to be specified as a child node to the SDIO controller

that connects the device to the system.

Required properties:

 - compatible : Should be "esp,esp8089".

Optional properties:

 - esp,crystal-26M-en: Integer value for the crystal_26M_en firmware parameter

Example:

&mmc1 {

	#address-cells = <1>;

	#size-cells = <0>;

	vmmc-supply = <&reg_dldo1>;

	mmc-pwrseq = <&wifi_pwrseq>;

	bus-width = <4>;

	non-removable;

	status = "okay";

	esp8089: sdio_wifi@1 {

		compatible = "esp,esp8089";

		reg = <1>;

		esp,crystal-26M-en = <2>;

	};

};

		compatible = "axis,artpec6-pcie", "snps,dw-pcie";

		reg = <0xf8050000 0x2000

		       0xf8040000 0x1000

		       0xc0000000 0x1000>;

		       0xc0000000 0x2000>;

		reg-names = "dbi", "phy", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

			  /* downstream I/O */

		ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000

		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000

			  /* non-prefetchable memory */

			  0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>;

			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;

		num-lanes = <2>;

		bus-range = <0x00 0xff>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;