Commit 87229ad9 authored Sep 19, 2012 by Dave Airlie Committed by Dave Airlie Sep 19, 2012

drm: micro optimise cache flushing



We hit this a lot with i915 and although we'd like to engineer things to hit
it a lot less, this commit at least makes it consume a few less cycles.

from something containing
movzwl 0x0(%rip),%r10d
to
add    %r8,%rdx

I only noticed it while using perf to profile something else.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>

parent f2032d41

drivers/gpu/drm/drm_cache.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -37,12 +37,13 @@ drm_clflush_page(struct page *page)
		{
		uint8_t *page_virtual;
		unsigned int i;
		const int size = boot_cpu_data.x86_clflush_size;

		if (unlikely(page == NULL))
		return;

		page_virtual = kmap_atomic(page);
		for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
		for (i = 0; i < PAGE_SIZE; i += size)
		clflush(page_virtual + i);
		kunmap_atomic(page_virtual);
		}