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Commit 8709b9eb authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Thomas Gleixner
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irqchip/gic: Add arm,pl390 support 



Add support for the PrimeCell® Generic Interrupt Controller (PL390) to
the GIC DT bindings and driver.

Currently the GIC driver treats this GIC variant the same as other GIC
variants, but there are differences in hardware topology (e.g. clock
inputs).

Sort the list of compatible values while we're at it.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarRob Herring <robh+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Link: http://lkml.kernel.org/r/1442261204-30931-2-git-send-email-geert%2Brenesas@glider.be


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 2a1d3ab8

Documentation/devicetree/bindings/arm/gic.txt

+5 −4
Original line number Original line Diff line number Diff line
@@ -11,13 +11,14 @@ have PPIs or SGIs. 
Main node required properties:

Main node required properties:





- compatible : should be one of:

- compatible : should be one of:

	"arm,gic-400"

	"arm,arm1176jzf-devchip-gic"

	"arm,arm11mp-gic"

	"arm,cortex-a15-gic"

	"arm,cortex-a15-gic"

	"arm,cortex-a9-gic"

	"arm,cortex-a7-gic"

	"arm,cortex-a7-gic"

	"arm,arm11mp-gic"

	"arm,cortex-a9-gic"

	"arm,gic-400"

	"arm,pl390"

	"brcm,brahma-b15-gic"

	"brcm,brahma-b15-gic"

	"arm,arm1176jzf-devchip-gic"

	"qcom,msm-8660-qgic"

	"qcom,msm-8660-qgic"

	"qcom,msm-qgic2"

	"qcom,msm-qgic2"

- interrupt-controller : Identifies the node as an interrupt controller

- interrupt-controller : Identifies the node as an interrupt controller

drivers/irqchip/irq-gic.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1191,6 +1191,7 @@ IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 
IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);

IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);

IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);

IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);

IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);





#endif

#endif