Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8695b612 authored by Alan Cox's avatar Alan Cox Committed by Dave Airlie
Browse files

gma500: Add the support of display port on CDV 



Import the pieces we need in order to do DisplayPort. Don't wire them
up yet as there is work to do to integrate them.

Signed-off-by: default avatarZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent d6676096

drivers/gpu/drm/gma500/cdv_intel_dp.c

0 → 100644
+1504 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/gma500/psb_intel_drv.h

+2 −4
Original line number Diff line number Diff line
@@ -29,10 +29,6 @@ 
 * Display related stuff

 */



/* store information about an Ixxx DVO */

/* The i830->i865 use multiple DVOs with multiple i2cs */

/* the i915, i945 have a single sDVO i2c bus - which is different */

#define MAX_OUTPUTS 6

/* maximum connectors per crtcs in the mode set */

#define INTELFB_CONN_LIMIT 4
@@ -69,6 +65,8 @@ 
#define INTEL_OUTPUT_HDMI 6

#define INTEL_OUTPUT_MIPI 7

#define INTEL_OUTPUT_MIPI2 8

#define INTEL_OUTPUT_DISPLAYPORT 9

#define INTEL_OUTPUT_EDP 10



#define INTEL_DVO_CHIP_NONE 0

#define INTEL_DVO_CHIP_LVDS 1

drivers/gpu/drm/gma500/psb_intel_reg.h

+155 −0
Original line number Diff line number Diff line
@@ -1347,5 +1347,160 @@ No status bits are changed. 
#define LANE_PLL_ENABLE		(0x3 << 20)

#define LANE_PLL_PIPE(p)	(((p) == 0) ? (1 << 21) : (0 << 21))



#define DP_B				0x64100

#define DP_C				0x64200



#define   DP_PORT_EN			(1 << 31)

#define   DP_PIPEB_SELECT		(1 << 30)

#define   DP_PIPE_MASK			(1 << 30)



/* Link training mode - select a suitable mode for each stage */

#define   DP_LINK_TRAIN_PAT_1		(0 << 28)

#define   DP_LINK_TRAIN_PAT_2		(1 << 28)

#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)

#define   DP_LINK_TRAIN_OFF		(3 << 28)

#define   DP_LINK_TRAIN_MASK		(3 << 28)

#define   DP_LINK_TRAIN_SHIFT		28



/* Signal voltages. These are mostly controlled by the other end */

#define   DP_VOLTAGE_0_4		(0 << 25)

#define   DP_VOLTAGE_0_6		(1 << 25)

#define   DP_VOLTAGE_0_8		(2 << 25)

#define   DP_VOLTAGE_1_2		(3 << 25)

#define   DP_VOLTAGE_MASK		(7 << 25)

#define   DP_VOLTAGE_SHIFT		25



/* Signal pre-emphasis levels, like voltages, the other end tells us what

 * they want

 */

#define   DP_PRE_EMPHASIS_0		(0 << 22)

#define   DP_PRE_EMPHASIS_3_5		(1 << 22)

#define   DP_PRE_EMPHASIS_6		(2 << 22)

#define   DP_PRE_EMPHASIS_9_5		(3 << 22)

#define   DP_PRE_EMPHASIS_MASK		(7 << 22)

#define   DP_PRE_EMPHASIS_SHIFT		22



/* How many wires to use. I guess 3 was too hard */

#define   DP_PORT_WIDTH_1		(0 << 19)

#define   DP_PORT_WIDTH_2		(1 << 19)

#define   DP_PORT_WIDTH_4		(3 << 19)

#define   DP_PORT_WIDTH_MASK		(7 << 19)



/* Mystic DPCD version 1.1 special mode */

#define   DP_ENHANCED_FRAMING		(1 << 18)



/** locked once port is enabled */

#define   DP_PORT_REVERSAL		(1 << 15)



/** sends the clock on lane 15 of the PEG for debug */

#define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)



#define   DP_SCRAMBLING_DISABLE		(1 << 12)

#define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)



/** limit RGB values to avoid confusing TVs */

#define   DP_COLOR_RANGE_16_235		(1 << 8)



/** Turn on the audio link */

#define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)



/** vs and hs sync polarity */

#define   DP_SYNC_VS_HIGH		(1 << 4)

#define   DP_SYNC_HS_HIGH		(1 << 3)



/** A fantasy */

#define   DP_DETECTED			(1 << 2)



/** The aux channel provides a way to talk to the

 * signal sink for DDC etc. Max packet size supported

 * is 20 bytes in each direction, hence the 5 fixed

 * data registers

 */

#define DPB_AUX_CH_CTL			0x64110

#define DPB_AUX_CH_DATA1		0x64114

#define DPB_AUX_CH_DATA2		0x64118

#define DPB_AUX_CH_DATA3		0x6411c

#define DPB_AUX_CH_DATA4		0x64120

#define DPB_AUX_CH_DATA5		0x64124



#define DPC_AUX_CH_CTL			0x64210

#define DPC_AUX_CH_DATA1		0x64214

#define DPC_AUX_CH_DATA2		0x64218

#define DPC_AUX_CH_DATA3		0x6421c

#define DPC_AUX_CH_DATA4		0x64220

#define DPC_AUX_CH_DATA5		0x64224



#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)

#define   DP_AUX_CH_CTL_DONE		    (1 << 30)

#define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)

#define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)

#define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)

#define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)

#define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)

#define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)

#define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)

#define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)

#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)

#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20

#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)

#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16

#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)

#define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)

#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)

#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)

#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)

#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)

#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0



/*

 * Computing GMCH M and N values for the Display Port link

 *

 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes

 *

 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)

 *

 * The GMCH value is used internally

 *

 * bytes_per_pixel is the number of bytes coming out of the plane,

 * which is after the LUTs, so we want the bytes for our color format.

 * For our current usage, this is always 3, one byte for R, G and B.

 */



#define _PIPEA_GMCH_DATA_M			0x70050

#define _PIPEB_GMCH_DATA_M			0x71050



/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */

#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)

#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25



#define   PIPE_GMCH_DATA_M_MASK			(0xffffff)



#define _PIPEA_GMCH_DATA_N			0x70054

#define _PIPEB_GMCH_DATA_N			0x71054

#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)



/*

 * Computing Link M and N values for the Display Port link

 *

 * Link M / N = pixel_clock / ls_clk

 *

 * (the DP spec calls pixel_clock the 'strm_clk')

 *

 * The Link value is transmitted in the Main Stream

 * Attributes and VB-ID.

 */



#define _PIPEA_DP_LINK_M				0x70060

#define _PIPEB_DP_LINK_M				0x71060

#define   PIPEA_DP_LINK_M_MASK			(0xffffff)



#define _PIPEA_DP_LINK_N				0x70064

#define _PIPEB_DP_LINK_N				0x71064

#define   PIPEA_DP_LINK_N_MASK			(0xffffff)



#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)

#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)

#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)

#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)



#endif