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Commit 851559e3 authored by Yan, Zheng's avatar Yan, Zheng Committed by Ingo Molnar
Browse files

perf/x86/intel: Use the PEBS auto reload mechanism when possible 



When a fixed period is specified, this patch makes perf use the PEBS
auto reload mechanism. This makes normal profiling faster, because
it avoids one costly MSR write in the PMI handler.

However, the reset value will be loaded by hardware assist. There is a
small delay compared to the previous non-auto-reload mechanism. The
delay time is arbitrary, but very small. The assist cost is 400-800
cycles, assuming common cases with everything cached. The minimum period
the patch currently uses is 10000. In that extreme case it can be ~10%
if cycles are used.

Signed-off-by: default avatarYan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: default avatarKan Liang <kan.liang@intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@infradead.org
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1430940834-8964-2-git-send-email-kan.liang@intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 5b68164d

arch/x86/kernel/cpu/perf_event.c

+9 −6
Original line number Diff line number Diff line
@@ -1094,6 +1094,8 @@ int x86_perf_event_set_period(struct perf_event *event) 


	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;



	if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||

	    local64_read(&hwc->prev_count) != (u64)-left) {

		/*

		 * The hw event starts counting from this event offset,

		 * mark it to be able to extra future deltas:
@@ -1101,6 +1103,7 @@ int x86_perf_event_set_period(struct perf_event *event) 
		local64_set(&hwc->prev_count, (u64)-left);



		wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);

	}



	/*

	 * Due to erratum on certan cpu we need

arch/x86/kernel/cpu/perf_event.h

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ struct event_constraint { 
#define PERF_X86_EVENT_DYNAMIC		0x0080 /* dynamic alloc'd constraint */

#define PERF_X86_EVENT_RDPMC_ALLOWED	0x0100 /* grant rdpmc permission */

#define PERF_X86_EVENT_EXCL_ACCT	0x0200 /* accounted EXCL event */

#define PERF_X86_EVENT_AUTO_RELOAD	0x0400 /* use PEBS auto-reload */





struct amd_nb {

arch/x86/kernel/cpu/perf_event_intel.c

+6 −2
Original line number Diff line number Diff line
@@ -2260,8 +2260,12 @@ static int intel_pmu_hw_config(struct perf_event *event) 
	if (ret)

		return ret;



	if (event->attr.precise_ip && x86_pmu.pebs_aliases)

	if (event->attr.precise_ip) {

		if (!event->attr.freq)

			event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;

		if (x86_pmu.pebs_aliases)

			x86_pmu.pebs_aliases(event);

	}



	if (needs_branch_stack(event)) {

		ret = intel_pmu_setup_lbr_filter(event);

arch/x86/kernel/cpu/perf_event_intel_ds.c

+7 −0
Original line number Diff line number Diff line
@@ -688,6 +688,7 @@ void intel_pmu_pebs_enable(struct perf_event *event) 
{

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	struct hw_perf_event *hwc = &event->hw;

	struct debug_store *ds = cpuc->ds;



	hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
@@ -697,6 +698,12 @@ void intel_pmu_pebs_enable(struct perf_event *event) 
		cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);

	else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)

		cpuc->pebs_enabled |= 1ULL << 63;



	/* Use auto-reload if possible to save a MSR write in the PMI */

	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {

		ds->pebs_event_reset[hwc->idx] =

			(u64)(-hwc->sample_period) & x86_pmu.cntval_mask;

	}

}



void intel_pmu_pebs_disable(struct perf_event *event)