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Commit 84a0ced0 authored by Pingchao Yang's avatar Pingchao Yang Committed by Herbert Xu
Browse files

crypto: qat - Change the definition of icp_qat_uof_regtype 



The definition of icp_qat_uof_regtype should be coherent with
 the definition in firmware compiler.

Signed-off-by: default avatarYang Pingchao <pingchao.yang@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent b93f342d

drivers/crypto/qat/qat_common/icp_qat_uclo.h

+21 −21
Original line number Diff line number Diff line
@@ -112,27 +112,27 @@ enum icp_qat_uof_mem_region { 
};



enum icp_qat_uof_regtype {

	ICP_NO_DEST,

	ICP_GPA_REL,

	ICP_GPA_ABS,

	ICP_GPB_REL,

	ICP_GPB_ABS,

	ICP_SR_REL,

	ICP_SR_RD_REL,

	ICP_SR_WR_REL,

	ICP_SR_ABS,

	ICP_SR_RD_ABS,

	ICP_SR_WR_ABS,

	ICP_DR_REL,

	ICP_DR_RD_REL,

	ICP_DR_WR_REL,

	ICP_DR_ABS,

	ICP_DR_RD_ABS,

	ICP_DR_WR_ABS,

	ICP_LMEM,

	ICP_LMEM0,

	ICP_LMEM1,

	ICP_NEIGH_REL,

	ICP_NO_DEST	= 0,

	ICP_GPA_REL	= 1,

	ICP_GPA_ABS	= 2,

	ICP_GPB_REL	= 3,

	ICP_GPB_ABS	= 4,

	ICP_SR_REL	= 5,

	ICP_SR_RD_REL	= 6,

	ICP_SR_WR_REL	= 7,

	ICP_SR_ABS	= 8,

	ICP_SR_RD_ABS	= 9,

	ICP_SR_WR_ABS	= 10,

	ICP_DR_REL	= 19,

	ICP_DR_RD_REL	= 20,

	ICP_DR_WR_REL	= 21,

	ICP_DR_ABS	= 22,

	ICP_DR_RD_ABS	= 23,

	ICP_DR_WR_ABS	= 24,

	ICP_LMEM	= 26,

	ICP_LMEM0	= 27,

	ICP_LMEM1	= 28,

	ICP_NEIGH_REL	= 31,

};



enum icp_qat_css_fwtype {