Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 846e438f authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Enable WoW only for AR9462



The only card with which WoW has been tested and verified is
AR9462. Do not enable it for all cards since WoW is really quirky
and needs to be tested properly with each chip.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 74a97755
Loading
Loading
Loading
Loading
+0 −4
Original line number Diff line number Diff line
@@ -38,10 +38,6 @@ static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
	else
		INIT_INI_ARRAY(&ah->iniPcieSerdes,
			   ar9280PciePhy_clkreq_always_on_L1_9280);
#ifdef CONFIG_PM_SLEEP
		INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
			       ar9280PciePhy_awow);
#endif

	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
+0 −14
Original line number Diff line number Diff line
@@ -925,20 +925,6 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
	{0x00004044, 0x00000000},
};

static const u32 ar9280PciePhy_awow[][2] = {
	/* Addr      allmodes  */
	{0x00004040, 0x9248fd00},
	{0x00004040, 0x24924924},
	{0x00004040, 0xa8000019},
	{0x00004040, 0x13160820},
	{0x00004040, 0xe5980560},
	{0x00004040, 0xc01dcffd},
	{0x00004040, 0x1aaabe41},
	{0x00004040, 0xbe105554},
	{0x00004040, 0x00043007},
	{0x00004044, 0x00000000},
};

static const u32 ar9285Modes_9285_1_2[][5] = {
	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+2 −7
Original line number Diff line number Diff line
@@ -2595,13 +2595,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
			pCap->hw_caps |= ATH9K_HW_CAP_RTT;
	}

	if (AR_SREV_9280_20_OR_LATER(ah)) {
		pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
				 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;

		if (AR_SREV_9280(ah))
			pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
	}
	if (AR_SREV_9462(ah))
		pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;

	if (AR_SREV_9300_20_OR_LATER(ah) &&
	    ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
+1 −8
Original line number Diff line number Diff line
@@ -246,9 +246,7 @@ enum ath9k_hw_caps {
	ATH9K_HW_CAP_MCI			= BIT(15),
	ATH9K_HW_CAP_DFS			= BIT(16),
	ATH9K_HW_WOW_DEVICE_CAPABLE		= BIT(17),
	ATH9K_HW_WOW_PATTERN_MATCH_EXACT	= BIT(18),
	ATH9K_HW_WOW_PATTERN_MATCH_DWORD	= BIT(19),
	ATH9K_HW_CAP_PAPRD			= BIT(20),
	ATH9K_HW_CAP_PAPRD			= BIT(18),
};

/*
@@ -882,9 +880,6 @@ struct ath_hw {
	struct ar5416IniArray iniBank6;
	struct ar5416IniArray iniAddac;
	struct ar5416IniArray iniPcieSerdes;
#ifdef CONFIG_PM_SLEEP
	struct ar5416IniArray iniPcieSerdesWow;
#endif
	struct ar5416IniArray iniPcieSerdesLowPower;
	struct ar5416IniArray iniModesFastClock;
	struct ar5416IniArray iniAdditional;
@@ -1165,8 +1160,6 @@ static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
}
#endif



#define ATH9K_CLOCK_RATE_CCK		22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
+0 −4
Original line number Diff line number Diff line
@@ -800,21 +800,17 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;

#ifdef CONFIG_PM_SLEEP

	if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
	    device_can_wakeup(sc->dev)) {

		hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
					  WIPHY_WOWLAN_DISCONNECT;
		hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN;
		hw->wiphy->wowlan.pattern_min_len = 1;
		hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE;

	}

	atomic_set(&sc->wow_sleep_proc_intr, -1);
	atomic_set(&sc->wow_got_bmiss_intr, -1);

#endif

	hw->queues = 4;
Loading