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Commit 83c17ba3 authored by LEROY Christophe's avatar LEROY Christophe Committed by Scott Wood
Browse files

powerpc/8xx: Use DAR to save r3 for CPU6 ERRATA 



As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent b0168eb9

arch/powerpc/kernel/head_8xx.S

+15 −18
Original line number Diff line number Diff line
@@ -83,13 +83,6 @@ _ENTRY(_start); 
 * 8M 1:1.  I also mapped an additional I/O space 1:1 so we can get to

 * the "internal" processor registers before MMU_init is called.

 *

 * The TLB code currently contains a major hack.  Since I use the condition

 * code register, I have to save and restore it.  I am out of registers, so

 * I just store it in memory location 0 (the TLB handlers are not reentrant).

 * To avoid making any decisions, I need to use the "segment" valid bit

 * in the first level table, but that would require many changes to the

 * Linux page directory/table functions that I don't want to do right now.

 *

 *	-- Dan

 */

	.globl	__start
@@ -306,7 +299,7 @@ SystemCall: 
 */

InstructionTLBMiss:

#ifdef CONFIG_8xx_CPU6

	stw	r3, 8(r0)

	mtspr	SPRN_DAR, r3

#endif

	EXCEPTION_PROLOG_0

	mtspr	SPRN_SPRG_SCRATCH2, r10
@@ -351,7 +344,10 @@ InstructionTLBMiss: 
#ifdef CONFIG_SWAP

	andi.	r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT

	cmpwi	cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT

	li	r11, RPN_PATTERN

	bne-	cr0, 2f

#else

	li	r11, RPN_PATTERN

#endif

	/* The Linux PTE won't go exactly into the MMU TLB.

	 * Software indicator bits 21 and 28 must be clear.
@@ -359,28 +355,29 @@ InstructionTLBMiss: 
	 * set.  All other Linux PTE bits control the behavior

	 * of the MMU.

	 */

	li	r11, RPN_PATTERN

	rlwimi	r10, r11, 0, 0x07f8	/* Set 24-27, clear 21-23,28 */

	MTSPR_CPU6(SPRN_MI_RPN, r10, r3)	/* Update TLB entry */



	/* Restore registers */

#ifdef CONFIG_8xx_CPU6

	lwz	r3, 8(r0)

	mfspr	r3, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

#endif

	mfspr	r10, SPRN_SPRG_SCRATCH2

	EXCEPTION_EPILOG_0

	rfi

2:

	mfspr	r11, SPRN_SRR1

	mfspr	r10, SPRN_SRR1

	/* clear all error bits as TLB Miss

	 * sets a few unconditionally

	*/

	rlwinm	r11, r11, 0, 0xffff

	mtspr	SPRN_SRR1, r11

	rlwinm	r10, r10, 0, 0xffff

	mtspr	SPRN_SRR1, r10



	/* Restore registers */

#ifdef CONFIG_8xx_CPU6

	lwz	r3, 8(r0)

	mfspr	r3, SPRN_DAR

	mtspr	SPRN_DAR, r11	/* Tag DAR */

#endif

	mfspr	r10, SPRN_SPRG_SCRATCH2

	b	InstructionTLBError1
@@ -388,7 +385,7 @@ InstructionTLBMiss: 
	. = 0x1200

DataStoreTLBMiss:

#ifdef CONFIG_8xx_CPU6

	stw	r3, 8(r0)

	mtspr	SPRN_DAR, r3

#endif

	EXCEPTION_PROLOG_0

	mtspr	SPRN_SPRG_SCRATCH2, r10
@@ -459,7 +456,7 @@ DataStoreTLBMiss: 


	/* Restore registers */

#ifdef CONFIG_8xx_CPU6

	lwz	r3, 8(r0)

	mfspr	r3, SPRN_DAR

#endif

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	mfspr	r10, SPRN_SPRG_SCRATCH2
@@ -531,7 +528,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */ 
#define NO_SELF_MODIFYING_CODE

FixupDAR:/* Entry point for dcbx workaround. */

#ifdef CONFIG_8xx_CPU6

	stw	r3, 8(r0)

	mtspr	SPRN_DAR, r3

#endif

	mtspr	SPRN_SPRG_SCRATCH2, r10

	/* fetch instruction from memory. */
@@ -550,7 +547,7 @@ FixupDAR:/* Entry point for dcbx workaround. */ 
	rlwinm	r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29

	lwzx	r11, r10, r11	/* Get the pte */

#ifdef CONFIG_8xx_CPU6

	lwz	r3, 8(r0)	/* restore r3 from memory */

	mfspr	r3, SPRN_DAR

#endif

	/* concat physical page address(r11) and page offset(r10) */

	mfspr	r10, SPRN_SRR0