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Commit 83112e68 authored by Andre Przywara's avatar Andre Przywara Committed by Ingo Molnar
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perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus 



With AMD cpu family 15h a unit mask was introduced for the Data Cache
Miss event (0x041/L1-dcache-load-misses). We need to enable bit 0
(first data cache miss or streaming store to a 64 B cache line) of
this mask to proper count data cache misses.

Now we set this bit for all families and models. In case a PMU does
not implement a unit mask for event 0x041 the bit is ignored.

Signed-off-by: default avatarAndre Przywara <andre.przywara@amd.com>
Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1302913676-14352-2-git-send-email-robert.richter@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 5d2cd909

arch/x86/kernel/cpu/perf_event_amd.c

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ static __initconst const u64 amd_hw_cache_event_ids 
 [ C(L1D) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */

		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */

		[ C(RESULT_MISS)   ] = 0x0141, /* Data Cache Misses          */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */