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Commit 81cc3f86 authored by Pawel Moll's avatar Pawel Moll Committed by Arnd Bergmann
Browse files

ARM: vexpress: Remove non-DT code 



Now, with the CLCD DT support available, there is no
more reason to keep the non-DT support for V2P-CA9.

Removed, together with "some" supporting code. It was
necessary to make PLAT_VERSATILE_SCHED_CLOCK optional
and selected by the machines still interested in it.

Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarPawel Moll <pawel.moll@arm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ad77b791

arch/arm/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -350,6 +350,7 @@ config ARCH_REALVIEW 
	select ICST

	select NEED_MACH_MEMORY_H

	select PLAT_VERSATILE

	select PLAT_VERSATILE_SCHED_CLOCK

	help

	  This enables support for ARM Ltd RealView boards.
@@ -365,6 +366,7 @@ config ARCH_VERSATILE 
	select ICST

	select PLAT_VERSATILE

	select PLAT_VERSATILE_CLOCK

	select PLAT_VERSATILE_SCHED_CLOCK

	select VERSATILE_FPGA_IRQ

	help

	  This enables support for ARM Ltd Versatile board.

arch/arm/mach-vexpress/Kconfig

+0 −3
Original line number Diff line number Diff line
@@ -49,9 +49,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA 
	  build a working kernel, you must also enable relevant core

	  tile support or Flattened Device Tree based support options.



config ARCH_VEXPRESS_CA9X4

	bool "Versatile Express Cortex-A9x4 tile"



config ARCH_VEXPRESS_DCSCB

	bool "Dual Cluster System Control Block (DCSCB) support"

	depends on MCPM

arch/arm/mach-vexpress/Makefile

+1 −2
Original line number Diff line number Diff line 
#

# Makefile for the linux kernel.

#

ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \

ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \

	-I$(srctree)/arch/arm/plat-versatile/include



obj-y					:= v2m.o

obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o

obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o	dcscb_setup.o

CFLAGS_dcscb.o				+= -march=armv7-a

CFLAGS_REMOVE_dcscb.o			= -pg

arch/arm/mach-vexpress/core.h

+0 −7
Original line number Diff line number Diff line 
/* 2MB large area for motherboard's peripherals static mapping */

#define V2M_PERIPH 0xf8000000



/* Tile's peripherals static mappings should start here */

#define V2T_PERIPH 0xf8200000



bool vexpress_smp_init_ops(void);



extern struct smp_operations	vexpress_smp_ops;

extern struct smp_operations	vexpress_smp_dt_ops;



extern void vexpress_cpu_die(unsigned int cpu);

arch/arm/mach-vexpress/ct-ca9x4.c

deleted100644 → 0
+0 −212
Original line number Diff line number Diff line 
/*

 * Versatile Express Core Tile Cortex A9x4 Support

 */

#include <linux/init.h>

#include <linux/gfp.h>

#include <linux/device.h>

#include <linux/dma-mapping.h>

#include <linux/platform_device.h>

#include <linux/amba/bus.h>

#include <linux/amba/clcd.h>

#include <linux/platform_data/video-clcd-versatile.h>

#include <linux/clkdev.h>

#include <linux/vexpress.h>

#include <linux/irqchip/arm-gic.h>



#include <asm/hardware/arm_timer.h>

#include <asm/hardware/cache-l2x0.h>

#include <asm/smp_scu.h>

#include <asm/smp_twd.h>



#include <mach/ct-ca9x4.h>



#include <asm/hardware/timer-sp.h>



#include <asm/mach/map.h>

#include <asm/mach/time.h>



#include "core.h"



#include <mach/motherboard.h>

#include <mach/irqs.h>



static struct map_desc ct_ca9x4_io_desc[] __initdata = {

	{

		.virtual        = V2T_PERIPH,

		.pfn            = __phys_to_pfn(CT_CA9X4_MPIC),

		.length         = SZ_8K,

		.type           = MT_DEVICE,

	},

};



static void __init ct_ca9x4_map_io(void)

{

	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));

}



static void __init ca9x4_l2_init(void)

{

#ifdef CONFIG_CACHE_L2X0

	void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);



	if (l2x0_base) {

		/* set RAM latencies to 1 cycle for this core tile. */

		writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);

		writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);



		l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);

	} else {

		pr_err("L2C: unable to map L2 cache controller\n");

	}

#endif

}



#ifdef CONFIG_HAVE_ARM_TWD

static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);



static void __init ca9x4_twd_init(void)

{

	int err = twd_local_timer_register(&twd_local_timer);

	if (err)

		pr_err("twd_local_timer_register failed %d\n", err);

}

#else

#define ca9x4_twd_init()	do {} while(0)

#endif



static void __init ct_ca9x4_init_irq(void)

{

	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),

		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));

	ca9x4_twd_init();

	ca9x4_l2_init();

}



static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)

{

	unsigned long framesize = 1024 * 768 * 2;



	fb->panel = versatile_clcd_get_panel("XVGA");

	if (!fb->panel)

		return -EINVAL;



	return versatile_clcd_setup_dma(fb, framesize);

}



static struct clcd_board ct_ca9x4_clcd_data = {

	.name		= "CT-CA9X4",

	.caps		= CLCD_CAP_5551 | CLCD_CAP_565,

	.check		= clcdfb_check,

	.decode		= clcdfb_decode,

	.setup		= ct_ca9x4_clcd_setup,

	.mmap		= versatile_clcd_mmap_dma,

	.remove		= versatile_clcd_remove_dma,

};



static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);

static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);

static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);

static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);



static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {

	&clcd_device,

	&dmc_device,

	&smc_device,

	&gpio_device,

};



static struct resource pmu_resources[] = {

	[0] = {

		.start	= IRQ_CT_CA9X4_PMU_CPU0,

		.end	= IRQ_CT_CA9X4_PMU_CPU0,

		.flags	= IORESOURCE_IRQ,

	},

	[1] = {

		.start	= IRQ_CT_CA9X4_PMU_CPU1,

		.end	= IRQ_CT_CA9X4_PMU_CPU1,

		.flags	= IORESOURCE_IRQ,

	},

	[2] = {

		.start	= IRQ_CT_CA9X4_PMU_CPU2,

		.end	= IRQ_CT_CA9X4_PMU_CPU2,

		.flags	= IORESOURCE_IRQ,

	},

	[3] = {

		.start	= IRQ_CT_CA9X4_PMU_CPU3,

		.end	= IRQ_CT_CA9X4_PMU_CPU3,

		.flags	= IORESOURCE_IRQ,

	},

};



static struct platform_device pmu_device = {

	.name		= "arm-pmu",

	.id		= -1,

	.num_resources	= ARRAY_SIZE(pmu_resources),

	.resource	= pmu_resources,

};



static struct clk_lookup osc1_lookup = {

	.dev_id		= "ct:clcd",

};



static struct platform_device osc1_device = {

	.name		= "vexpress-osc",

	.id		= 1,

	.num_resources	= 1,

	.resource	= (struct resource []) {

		VEXPRESS_RES_FUNC(0xf, 1),

	},

	.dev.platform_data = &osc1_lookup,

};



static void __init ct_ca9x4_init(void)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)

		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);



	platform_device_register(&pmu_device);

	vexpress_syscfg_device_register(&osc1_device);

}



#ifdef CONFIG_SMP

static void *ct_ca9x4_scu_base __initdata;



static void __init ct_ca9x4_init_cpu_map(void)

{

	int i, ncores;



	ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);

	if (WARN_ON(!ct_ca9x4_scu_base))

		return;



	ncores = scu_get_core_count(ct_ca9x4_scu_base);



	if (ncores > nr_cpu_ids) {

		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",

			ncores, nr_cpu_ids);

		ncores = nr_cpu_ids;

	}



	for (i = 0; i < ncores; ++i)

		set_cpu_possible(i, true);

}



static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)

{

	scu_enable(ct_ca9x4_scu_base);

}

#endif



struct ct_desc ct_ca9x4_desc __initdata = {

	.id		= V2M_CT_ID_CA9,

	.name		= "CA9x4",

	.map_io		= ct_ca9x4_map_io,

	.init_irq	= ct_ca9x4_init_irq,

	.init_tile	= ct_ca9x4_init,

#ifdef CONFIG_SMP

	.init_cpu_map	= ct_ca9x4_init_cpu_map,

	.smp_enable	= ct_ca9x4_smp_enable,

#endif

};