Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 816242da authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Add boot option to force UltraSPARC-III P-Cache on. 



Older UltraSPARC-III chips have a P-Cache bug that makes us disable it
by default at boot time.

However, this does hurt performance substantially, particularly with
memcpy(), and the bug is _incredibly_ obscure.  I have never seen it
triggered in practice, ever.

So provide a "-P" boot option that forces the P-Cache on.  It taints
the kernel, so if it does trigger and cause some data corruption or
OOPS, we will find out in the logs that this option was on when it
happened.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ab3fc403

arch/sparc64/kernel/setup.c

+11 −0
Original line number Diff line number Diff line
@@ -383,6 +383,17 @@ static void __init process_switch(char c) 
		/* Use PROM debug console. */

		register_console(&prom_debug_console);

		break;

	case 'P':

		/* Force UltraSPARC-III P-Cache on. */

		if (tlb_type != cheetah) {

			printk("BOOT: Ignoring P-Cache force option.\n");

			break;

		}

		cheetah_pcache_forced_on = 1;

		add_taint(TAINT_MACHINE_CHECK);

		cheetah_enable_pcache();

		break;



	default:

		printk("Unknown boot switch (-%c)\n", c);

		break;

arch/sparc64/kernel/smp.c

+3 −0
Original line number Diff line number Diff line
@@ -123,6 +123,9 @@ void __init smp_callin(void) 


	smp_setup_percpu_timer();



	if (cheetah_pcache_forced_on)

		cheetah_enable_pcache();



	local_irq_enable();



	calibrate_delay();

arch/sparc64/kernel/traps.c

+19 −0
Original line number Diff line number Diff line
@@ -421,6 +421,25 @@ asmlinkage void cee_log(unsigned long ce_status, 
	}

}



int cheetah_pcache_forced_on;



void cheetah_enable_pcache(void)

{

	unsigned long dcr;



	printk("CHEETAH: Enabling P-Cache on cpu %d.\n",

	       smp_processor_id());



	__asm__ __volatile__("ldxa [%%g0] %1, %0"

			     : "=r" (dcr)

			     : "i" (ASI_DCU_CONTROL_REG));

	dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);

	__asm__ __volatile__("stxa %0, [%%g0] %1\n\t"

			     "membar #Sync"

			     : /* no outputs */

			     : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));

}



/* Cheetah error trap handling. */

static unsigned long ecache_flush_physbase;

static unsigned long ecache_flush_linesize;

include/asm-sparc64/spitfire.h

+3 −0
Original line number Diff line number Diff line
@@ -48,6 +48,9 @@ enum ultra_tlb_layout { 


extern enum ultra_tlb_layout tlb_type;



extern int cheetah_pcache_forced_on;

extern void cheetah_enable_pcache(void);



#define sparc64_highest_locked_tlbent()	\

	(tlb_type == spitfire ? \

	 SPITFIRE_HIGHEST_LOCKED_TLBENT : \