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Commit 8090ba8c authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915: Apply the PPS register unlock workaround more consistently 



Atm, we apply this workaround somewhat inconsistently at the following
points: driver loading, LVDS init, eDP PPS init, system resume. As this
workaround also affects registers other than PPS (timing, PLL) a more
consistent way is to apply it early after the PPS HW context is known to
be lost: driver loading, system resume and on VLV/CHV/BXT when turning
on power domains.

This is needed by the next patch that removes saving/restoring of the
PP_CONTROL register.

This also removes the incorrect programming of the workaround on HSW+
PCH platforms which don't have the register locking mechanism.

v2: (Ville)
- Don't apply the workaround on BXT.
- Simplify platform checks using HAS_DDI().
v3:
- Move the call of intel_pps_unlock_regs_wa() to the more
  logical vlv_display_power_well_init() (also fixing CHV) (Ville).

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470827254-21954-5-git-send-email-imre.deak@intel.com
parent 335f752b

drivers/gpu/drm/i915/i915_drv.c

+1 −0
Original line number Diff line number Diff line
@@ -1560,6 +1560,7 @@ static int i915_drm_resume(struct drm_device *dev) 
	i915_gem_resume(dev);



	i915_restore_state(dev);

	intel_pps_unlock_regs_wa(dev_priv);

	intel_opregion_setup(dev_priv);



	intel_init_pch_refclk(dev);

drivers/gpu/drm/i915/intel_display.c

+26 −0
Original line number Diff line number Diff line
@@ -14729,6 +14729,30 @@ static bool intel_crt_present(struct drm_device *dev) 
	return true;

}



void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)

{

	int pps_num;

	int pps_idx;



	if (HAS_DDI(dev_priv))

		return;

	/*

	 * This w/a is needed at least on CPT/PPT, but to be sure apply it

	 * everywhere where registers can be write protected.

	 */

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		pps_num = 2;

	else

		pps_num = 1;



	for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {

		u32 val = I915_READ(PP_CONTROL(pps_idx));



		val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;

		I915_WRITE(PP_CONTROL(pps_idx), val);

	}

}



static void intel_pps_init(struct drm_i915_private *dev_priv)

{

	if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
@@ -14737,6 +14761,8 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) 
		dev_priv->pps_mmio_base = VLV_PPS_BASE;

	else

		dev_priv->pps_mmio_base = PPS_BASE;



	intel_pps_unlock_regs_wa(dev_priv);

}



static void intel_setup_outputs(struct drm_device *dev)

drivers/gpu/drm/i915/intel_dp.c

+2 −1
Original line number Diff line number Diff line
@@ -1829,7 +1829,8 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 
	lockdep_assert_held(&dev_priv->pps_mutex);



	control = I915_READ(_pp_ctrl_reg(intel_dp));

	if (!IS_BROXTON(dev)) {

	if (WARN_ON(!HAS_DDI(dev_priv) &&

		    (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {

		control &= ~PANEL_UNLOCK_MASK;

		control |= PANEL_UNLOCK_REGS;

	}

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1162,6 +1162,7 @@ void intel_mark_busy(struct drm_i915_private *dev_priv); 
void intel_mark_idle(struct drm_i915_private *dev_priv);

void intel_crtc_restore_mode(struct drm_crtc *crtc);

int intel_display_suspend(struct drm_device *dev);

void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);

void intel_encoder_destroy(struct drm_encoder *encoder);

int intel_connector_init(struct intel_connector *);

struct intel_connector *intel_connector_alloc(void);

drivers/gpu/drm/i915/intel_lvds.c

+0 −8
Original line number Diff line number Diff line
@@ -978,14 +978,6 @@ void intel_lvds_init(struct drm_device *dev) 
	int pipe;

	u8 pin;



	/*

	 * Unlock registers and just leave them unlocked. Do this before

	 * checking quirk lists to avoid bogus WARNINGs.

	 */

	if (HAS_PCH_SPLIT(dev_priv) || INTEL_GEN(dev_priv) <= 4)

		I915_WRITE(PP_CONTROL(0),

			   I915_READ(PP_CONTROL(0)) | PANEL_UNLOCK_REGS);



	if (!intel_lvds_supported(dev))

		return;