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Commit 80605c65 authored by John Fastabend's avatar John Fastabend Committed by Jeff Kirsher
Browse files

ixgbe: consolidate packet buffer allocation 



Consolidate packet buffer allocation currently being
done in the DCB path and main path. This allows the
feature set and packet buffer requirements to be done
once.

This is prep work to allow DCB to coexist with other
features namely, flow director.

CC: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJohn Fastabend <john.r.fastabend@intel.com>
Tested-by: default avatarRoss Brattain <ross.b.brattain@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 1fcd86b5

drivers/net/ixgbe/ixgbe_82598.c

+42 −0
Original line number Diff line number Diff line
@@ -1242,6 +1242,47 @@ static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 
	}

}



/**

 * ixgbe_set_rxpba_82598 - Configure packet buffers

 * @hw: pointer to hardware structure

 * @dcb_config: pointer to ixgbe_dcb_config structure

 *

 * Configure packet buffers.

 */

static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,

				  int strategy)

{

	u32 rxpktsize = IXGBE_RXPBSIZE_64KB;

	u8  i = 0;



	if (!num_pb)

		return;



	/* Setup Rx packet buffer sizes */

	switch (strategy) {

	case PBA_STRATEGY_WEIGHTED:

		/* Setup the first four at 80KB */

		rxpktsize = IXGBE_RXPBSIZE_80KB;

		for (; i < 4; i++)

			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);

		/* Setup the last four at 48KB...don't re-init i */

		rxpktsize = IXGBE_RXPBSIZE_48KB;

		/* Fall Through */

	case PBA_STRATEGY_EQUAL:

	default:

		/* Divide the remaining Rx packet buffer evenly among the TCs */

		for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)

			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);

		break;

	}



	/* Setup Tx packet buffer sizes */

	for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)

		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);



	return;

}



static struct ixgbe_mac_operations mac_ops_82598 = {

	.init_hw		= &ixgbe_init_hw_generic,

	.reset_hw		= &ixgbe_reset_hw_82598,
@@ -1257,6 +1298,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = { 
	.read_analog_reg8	= &ixgbe_read_analog_reg8_82598,

	.write_analog_reg8	= &ixgbe_write_analog_reg8_82598,

	.setup_link		= &ixgbe_setup_mac_link_82598,

	.set_rxpba		= &ixgbe_set_rxpba_82598,

	.check_link		= &ixgbe_check_mac_link_82598,

	.get_link_capabilities	= &ixgbe_get_link_capabilities_82598,

	.led_on			= &ixgbe_led_on_generic,

drivers/net/ixgbe/ixgbe_82599.c

+1 −38
Original line number Diff line number Diff line
@@ -1114,27 +1114,8 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 
s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)

{

	u32 fdirctrl = 0;

	u32 pbsize;

	int i;



	/*

	 * Before enabling Flow Director, the Rx Packet Buffer size

	 * must be reduced.  The new value is the current size minus

	 * flow director memory usage size.

	 */

	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));

	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),

	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));



	/*

	 * The defaults in the HW for RX PB 1-7 are not zero and so should be

	 * initialized to zero for non DCB mode otherwise actual total RX PB

	 * would be bigger than programmed and filter space would run into

	 * the PB 0 region.

	 */

	for (i = 1; i < 8; i++)

		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);



	/* Send interrupt when 64 filters are left */

	fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
@@ -1202,27 +1183,8 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 
s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)

{

	u32 fdirctrl = 0;

	u32 pbsize;

	int i;



	/*

	 * Before enabling Flow Director, the Rx Packet Buffer size

	 * must be reduced.  The new value is the current size minus

	 * flow director memory usage size.

	 */

	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));

	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),

	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));



	/*

	 * The defaults in the HW for RX PB 1-7 are not zero and so should be

	 * initialized to zero for non DCB mode otherwise actual total RX PB

	 * would be bigger than programmed and filter space would run into

	 * the PB 0 region.

	 */

	for (i = 1; i < 8; i++)

		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);



	/* Send interrupt when 64 filters are left */

	fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
@@ -2146,6 +2108,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = { 
	.read_analog_reg8       = &ixgbe_read_analog_reg8_82599,

	.write_analog_reg8      = &ixgbe_write_analog_reg8_82599,

	.setup_link             = &ixgbe_setup_mac_link_82599,

	.set_rxpba		= &ixgbe_set_rxpba_generic,

	.check_link             = &ixgbe_check_mac_link_generic,

	.get_link_capabilities  = &ixgbe_get_link_capabilities_82599,

	.led_on                 = &ixgbe_led_on_generic,

drivers/net/ixgbe/ixgbe_common.c

+66 −0
Original line number Diff line number Diff line
@@ -3267,3 +3267,69 @@ s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 


	return 0;

}



/**

 * ixgbe_set_rxpba_generic - Initialize RX packet buffer

 * @hw: pointer to hardware structure

 * @num_pb: number of packet buffers to allocate

 * @headroom: reserve n KB of headroom

 * @strategy: packet buffer allocation strategy

 **/

void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,

			     int num_pb,

			     u32 headroom,

			     int strategy)

{

	u32 pbsize = hw->mac.rx_pb_size;

	int i = 0;

	u32 rxpktsize, txpktsize, txpbthresh;



	/* Reserve headroom */

	pbsize -= headroom;



	if (!num_pb)

		num_pb = 1;



	/* Divide remaining packet buffer space amongst the number

	 * of packet buffers requested using supplied strategy.

	 */

	switch (strategy) {

	case (PBA_STRATEGY_WEIGHTED):

		/* pba_80_48 strategy weight first half of packet buffer with

		 * 5/8 of the packet buffer space.

		 */

		rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));

		pbsize -= rxpktsize * (num_pb / 2);

		rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;

		for (; i < (num_pb / 2); i++)

			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);

		/* Fall through to configure remaining packet buffers */

	case (PBA_STRATEGY_EQUAL):

		/* Divide the remaining Rx packet buffer evenly among the TCs */

		rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;

		for (; i < num_pb; i++)

			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);

		break;

	default:

		break;

	}



	/*

	 * Setup Tx packet buffer and threshold equally for all TCs

	 * TXPBTHRESH register is set in K so divide by 1024 and subtract

	 * 10 since the largest packet we support is just over 9K.

	 */

	txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;

	txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;

	for (i = 0; i < num_pb; i++) {

		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);

		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);

	}



	/* Clear unused TCs, if any, to zero buffer size*/

	for (; i < IXGBE_MAX_PB; i++) {

		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);

		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);

		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);

	}

}

drivers/net/ixgbe/ixgbe_common.h

+3 −0
Original line number Diff line number Diff line
@@ -100,6 +100,9 @@ void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf); 
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);

s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);



void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,

			     u32 headroom, int strategy);



#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))



#ifndef writeq

drivers/net/ixgbe/ixgbe_dcb.c

+4 −6
Original line number Diff line number Diff line
@@ -258,15 +258,13 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, 


	switch (hw->mac.type) {

	case ixgbe_mac_82598EB:

		ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->rx_pba_cfg,

						pfc_en, refill, max, bwgid,

						ptype);

		ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,

						bwgid, ptype);

		break;

	case ixgbe_mac_82599EB:

	case ixgbe_mac_X540:

		ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,

						pfc_en, refill, max, bwgid,

						ptype, prio_tc);

		ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,

						bwgid, ptype, prio_tc);

		break;

	default:

		break;