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Commit 804c7559 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add additional safe regs for r4xx/rs6xx and r5xx 



- r4xx/rs6xx: add support for extended pixel shader
instruction/temp regs
- r5xx: add SM3 regs

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 003e69f9

drivers/gpu/drm/radeon/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable 
$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable

	$(call if_changed,mkregtable)



$(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable

	$(call if_changed,mkregtable)



$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable

	$(call if_changed,mkregtable)
@@ -35,6 +38,8 @@ $(obj)/rv515.o: $(obj)/rv515_reg_safe.h 


$(obj)/r300.o: $(obj)/r300_reg_safe.h



$(obj)/r420.o: $(obj)/r420_reg_safe.h



$(obj)/rs600.o: $(obj)/rs600_reg_safe.h



radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \

drivers/gpu/drm/radeon/r420.c

+8 −1
Original line number Diff line number Diff line
@@ -32,6 +32,13 @@ 
#include "atom.h"

#include "r100d.h"

#include "r420d.h"

#include "r420_reg_safe.h"



static void r420_set_reg_safe(struct radeon_device *rdev)

{

	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;

	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);

}



int r420_mc_init(struct radeon_device *rdev)

{
@@ -378,7 +385,7 @@ int r420_init(struct radeon_device *rdev) 
		if (r)

			return r;

	}

	r300_set_reg_safe(rdev);

	r420_set_reg_safe(rdev);

	rdev->accel_working = true;

	r = r420_startup(rdev);

	if (r) {

drivers/gpu/drm/radeon/reg_srcs/r420

0 → 100644
+795 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/reg_srcs/rs600

+67 −1
Original line number Diff line number Diff line
@@ -291,6 +291,8 @@ rs600 0x6d40 
0x46AC US_OUT_FMT_2

0x46B0 US_OUT_FMT_3

0x46B4 US_W_FMT

0x46B8 US_CODE_BANK

0x46BC US_CODE_EXT

0x46C0 US_ALU_RGB_ADDR_0

0x46C4 US_ALU_RGB_ADDR_1

0x46C8 US_ALU_RGB_ADDR_2
@@ -547,6 +549,70 @@ rs600 0x6d40 
0x4AB4 US_ALU_ALPHA_INST_61

0x4AB8 US_ALU_ALPHA_INST_62

0x4ABC US_ALU_ALPHA_INST_63

0x4AC0 US_ALU_EXT_ADDR_0

0x4AC4 US_ALU_EXT_ADDR_1

0x4AC8 US_ALU_EXT_ADDR_2

0x4ACC US_ALU_EXT_ADDR_3

0x4AD0 US_ALU_EXT_ADDR_4

0x4AD4 US_ALU_EXT_ADDR_5

0x4AD8 US_ALU_EXT_ADDR_6

0x4ADC US_ALU_EXT_ADDR_7

0x4AE0 US_ALU_EXT_ADDR_8

0x4AE4 US_ALU_EXT_ADDR_9

0x4AE8 US_ALU_EXT_ADDR_10

0x4AEC US_ALU_EXT_ADDR_11

0x4AF0 US_ALU_EXT_ADDR_12

0x4AF4 US_ALU_EXT_ADDR_13

0x4AF8 US_ALU_EXT_ADDR_14

0x4AFC US_ALU_EXT_ADDR_15

0x4B00 US_ALU_EXT_ADDR_16

0x4B04 US_ALU_EXT_ADDR_17

0x4B08 US_ALU_EXT_ADDR_18

0x4B0C US_ALU_EXT_ADDR_19

0x4B10 US_ALU_EXT_ADDR_20

0x4B14 US_ALU_EXT_ADDR_21

0x4B18 US_ALU_EXT_ADDR_22

0x4B1C US_ALU_EXT_ADDR_23

0x4B20 US_ALU_EXT_ADDR_24

0x4B24 US_ALU_EXT_ADDR_25

0x4B28 US_ALU_EXT_ADDR_26

0x4B2C US_ALU_EXT_ADDR_27

0x4B30 US_ALU_EXT_ADDR_28

0x4B34 US_ALU_EXT_ADDR_29

0x4B38 US_ALU_EXT_ADDR_30

0x4B3C US_ALU_EXT_ADDR_31

0x4B40 US_ALU_EXT_ADDR_32

0x4B44 US_ALU_EXT_ADDR_33

0x4B48 US_ALU_EXT_ADDR_34

0x4B4C US_ALU_EXT_ADDR_35

0x4B50 US_ALU_EXT_ADDR_36

0x4B54 US_ALU_EXT_ADDR_37

0x4B58 US_ALU_EXT_ADDR_38

0x4B5C US_ALU_EXT_ADDR_39

0x4B60 US_ALU_EXT_ADDR_40

0x4B64 US_ALU_EXT_ADDR_41

0x4B68 US_ALU_EXT_ADDR_42

0x4B6C US_ALU_EXT_ADDR_43

0x4B70 US_ALU_EXT_ADDR_44

0x4B74 US_ALU_EXT_ADDR_45

0x4B78 US_ALU_EXT_ADDR_46

0x4B7C US_ALU_EXT_ADDR_47

0x4B80 US_ALU_EXT_ADDR_48

0x4B84 US_ALU_EXT_ADDR_49

0x4B88 US_ALU_EXT_ADDR_50

0x4B8C US_ALU_EXT_ADDR_51

0x4B90 US_ALU_EXT_ADDR_52

0x4B94 US_ALU_EXT_ADDR_53

0x4B98 US_ALU_EXT_ADDR_54

0x4B9C US_ALU_EXT_ADDR_55

0x4BA0 US_ALU_EXT_ADDR_56

0x4BA4 US_ALU_EXT_ADDR_57

0x4BA8 US_ALU_EXT_ADDR_58

0x4BAC US_ALU_EXT_ADDR_59

0x4BB0 US_ALU_EXT_ADDR_60

0x4BB4 US_ALU_EXT_ADDR_61

0x4BB8 US_ALU_EXT_ADDR_62

0x4BBC US_ALU_EXT_ADDR_63

0x4BC0 FG_FOG_BLEND

0x4BC4 FG_FOG_FACTOR

0x4BC8 FG_FOG_COLOR_R

drivers/gpu/drm/radeon/reg_srcs/rv515

+6 −0
Original line number Diff line number Diff line
@@ -161,7 +161,12 @@ rv515 0x6d40 
0x401C GB_SELECT

0x4020 GB_AA_CONFIG

0x4024 GB_FIFO_SIZE

0x4028 GB_Z_PEQ_CONFIG

0x4100 TX_INVALTAGS

0x4114 SU_TEX_WRAP_PS3

0x4118 PS3_ENABLE

0x411c PS3_VTX_FMT

0x4120 PS3_TEX_SOURCE

0x4200 GA_POINT_S0

0x4204 GA_POINT_T0

0x4208 GA_POINT_S1
@@ -171,6 +176,7 @@ rv515 0x6d40 
0x4230 GA_POINT_MINMAX

0x4234 GA_LINE_CNTL

0x4238 GA_LINE_STIPPLE_CONFIG

0x4258 GA_COLOR_CONTROL_PS3

0x4260 GA_LINE_STIPPLE_VALUE

0x4264 GA_LINE_S0

0x4268 GA_LINE_S1