Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7f88da0c authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bdw: Limit SDE poly depth FIFO to 2 



BDW-A workaround

BDW Bug #1899155

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bf66347c

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -783,6 +783,7 @@ 
#define _3D_CHICKEN3	0x02090

#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)

#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)

#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1)



#define MI_MODE		0x0209c

# define VS_TIMER_DISPATCH				(1 << 6)

drivers/gpu/drm/i915/intel_pm.c

+3 −0
Original line number Diff line number Diff line
@@ -5294,6 +5294,9 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));

	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));



	I915_WRITE(_3D_CHICKEN3,

		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));



	/* WaSwitchSolVfFArbitrationPriority */

	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);