Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7e37f889 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Rename struct intel_ringbuffer to struct intel_ring



The state stored in this struct is not only the information about the
buffer object, but the ring used to communicate with the hardware. Using
buffer here is overly specific and, for me at least, conflates with the
notion of buffer objects themselves.

s/struct intel_ringbuffer/struct intel_ring/
s/enum intel_ring_hangcheck/enum intel_engine_hangcheck/
s/describe_ctx_ringbuf()/describe_ctx_ring()/
s/intel_ring_get_active_head()/intel_engine_get_active_head()/
s/intel_ring_sync_index()/intel_engine_sync_index()/
s/intel_ring_init_seqno()/intel_engine_init_seqno()/
s/ring_stuck()/engine_stuck()/
s/intel_cleanup_engine()/intel_engine_cleanup()/
s/intel_stop_engine()/intel_engine_stop()/
s/intel_pin_and_map_ringbuffer_obj()/intel_pin_and_map_ring()/
s/intel_unpin_ringbuffer()/intel_unpin_ring()/
s/intel_engine_create_ringbuffer()/intel_engine_create_ring()/
s/intel_ring_flush_all_caches()/intel_engine_flush_all_caches()/
s/intel_ring_invalidate_all_caches()/intel_engine_invalidate_all_caches()/
s/intel_ringbuffer_free()/intel_ring_free()/

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-15-git-send-email-chris@chris-wilson.co.uk
Link: http://patchwork.freedesktop.org/patch/msgid/1470174640-18242-4-git-send-email-chris@chris-wilson.co.uk
parent dca33ecc
Loading
Loading
Loading
Loading
+5 −6
Original line number Diff line number Diff line
@@ -1419,7 +1419,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
	intel_runtime_pm_get(dev_priv);

	for_each_engine_id(engine, dev_priv, id) {
		acthd[id] = intel_ring_get_active_head(engine);
		acthd[id] = intel_engine_get_active_head(engine);
		seqno[id] = intel_engine_get_seqno(engine);
	}

@@ -2036,12 +2036,11 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
	return 0;
}

static void describe_ctx_ringbuf(struct seq_file *m,
				 struct intel_ringbuffer *ringbuf)
static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
{
	seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
		   ringbuf->space, ringbuf->head, ringbuf->tail,
		   ringbuf->last_retired_head);
		   ring->space, ring->head, ring->tail,
		   ring->last_retired_head);
}

static int i915_context_status(struct seq_file *m, void *unused)
@@ -2086,7 +2085,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
			if (ce->state)
				describe_obj(m, ce->state);
			if (ce->ring)
				describe_ctx_ringbuf(m, ce->ring);
				describe_ctx_ring(m, ce->ring);
			seq_putc(m, '\n');
		}

+2 −2
Original line number Diff line number Diff line
@@ -518,7 +518,7 @@ struct drm_i915_error_state {
		bool waiting;
		int num_waiters;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		enum intel_engine_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
@@ -894,7 +894,7 @@ struct i915_gem_context {

	struct intel_context {
		struct drm_i915_gem_object *state;
		struct intel_ringbuffer *ring;
		struct intel_ring *ring;
		struct i915_vma *lrc_vma;
		uint32_t *lrc_reg_state;
		u64 lrc_desc;
+8 −8
Original line number Diff line number Diff line
@@ -2486,7 +2486,7 @@ static void i915_gem_reset_engine_status(struct intel_engine_cs *engine)

static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
{
	struct intel_ringbuffer *buffer;
	struct intel_ring *ring;

	while (!list_empty(&engine->active_list)) {
		struct drm_i915_gem_object *obj;
@@ -2502,7 +2502,7 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
	 * (lockless) lookup doesn't try and wait upon the request as we
	 * reset it.
	 */
	intel_ring_init_seqno(engine, engine->last_submitted_seqno);
	intel_engine_init_seqno(engine, engine->last_submitted_seqno);

	/*
	 * Clear the execlists queue up before freeing the requests, as those
@@ -2541,9 +2541,9 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
	 * upon reset is less than when we start. Do one more pass over
	 * all the ringbuffers to reset last_retired_head.
	 */
	list_for_each_entry(buffer, &engine->buffers, link) {
		buffer->last_retired_head = buffer->tail;
		intel_ring_update_space(buffer);
	list_for_each_entry(ring, &engine->buffers, link) {
		ring->last_retired_head = ring->tail;
		intel_ring_update_space(ring);
	}

	engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
@@ -2870,7 +2870,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,

		i915_gem_object_retire_request(obj, from_req);
	} else {
		int idx = intel_ring_sync_index(from, to);
		int idx = intel_engine_sync_index(from, to);
		u32 seqno = i915_gem_request_get_seqno(from_req);

		WARN_ON(!to_req);
@@ -4570,8 +4570,8 @@ int i915_gem_init(struct drm_device *dev)

	if (!i915.enable_execlists) {
		dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
		dev_priv->gt.cleanup_engine = intel_cleanup_engine;
		dev_priv->gt.stop_engine = intel_stop_engine;
		dev_priv->gt.cleanup_engine = intel_engine_cleanup;
		dev_priv->gt.stop_engine = intel_engine_stop;
	} else {
		dev_priv->gt.execbuf_submit = intel_execlists_submission;
		dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
+3 −3
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ void i915_gem_context_free(struct kref *ctx_ref)

		WARN_ON(ce->pin_count);
		if (ce->ring)
			intel_ringbuffer_free(ce->ring);
			intel_ring_free(ce->ring);

		i915_gem_object_put(ce->state);
	}
@@ -552,7 +552,7 @@ static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
	struct drm_i915_private *dev_priv = req->i915;
	struct intel_ringbuffer *ring = req->ring;
	struct intel_ring *ring = req->ring;
	struct intel_engine_cs *engine = req->engine;
	u32 flags = hw_flags | MI_MM_SPACE_GTT;
	const int num_rings =
@@ -655,7 +655,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
static int remap_l3(struct drm_i915_gem_request *req, int slice)
{
	u32 *remap_info = req->i915->l3_parity.remap_info[slice];
	struct intel_ringbuffer *ring = req->ring;
	struct intel_ring *ring = req->ring;
	int i, ret;

	if (!remap_info)
+3 −3
Original line number Diff line number Diff line
@@ -1001,7 +1001,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
	/* Unconditionally invalidate gpu caches and ensure that we do flush
	 * any residual writes from the previous batch.
	 */
	return intel_ring_invalidate_all_caches(req);
	return intel_engine_invalidate_all_caches(req);
}

static bool
@@ -1173,7 +1173,7 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
static int
i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
	struct intel_ringbuffer *ring = req->ring;
	struct intel_ring *ring = req->ring;
	int ret, i;

	if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
@@ -1303,7 +1303,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,

	if (params->engine->id == RCS &&
	    instp_mode != dev_priv->relative_constants_mode) {
		struct intel_ringbuffer *ring = params->request->ring;
		struct intel_ring *ring = params->request->ring;

		ret = intel_ring_begin(params->request, 4);
		if (ret)
Loading