Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7e0810c9 authored by Sylvain Lemieux's avatar Sylvain Lemieux Committed by Stephen Boyd
Browse files

clk: lpc32xx: add HCLK PLL output configuration 



This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.

If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.

The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.

Signed-off-by: default avatarSylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 58bb6215

drivers/clk/nxp/clk-lpc32xx.c

+1 −5
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ enum { 


enum {

	/* Start from the last defined clock in dt bindings */

	LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_ADC + 1,

	LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_HCLK_PLL + 1,

	LPC32XX_CLK_ADC_RTC,

	LPC32XX_CLK_TEST1,

	LPC32XX_CLK_TEST2,
@@ -96,7 +96,6 @@ enum { 
	LPC32XX_CLK_OSC,

	LPC32XX_CLK_SYS,

	LPC32XX_CLK_PLL397X,

	LPC32XX_CLK_HCLK_PLL,

	LPC32XX_CLK_HCLK_DIV_PERIPH,

	LPC32XX_CLK_HCLK_DIV,

	LPC32XX_CLK_HCLK,
@@ -1526,9 +1525,6 @@ static void __init lpc32xx_clk_init(struct device_node *np) 


	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);



	/* For 13MHz osc valid output range of PLL is from 156MHz to 266.5MHz */

	clk_set_rate(clk[LPC32XX_CLK_HCLK_PLL], 208000000);



	/* Set 48MHz rate of USB PLL clock */

	clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);

include/dt-bindings/clock/lpc32xx-clock.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#define LPC32XX_CLK_PWM1	32

#define LPC32XX_CLK_PWM2	33

#define LPC32XX_CLK_ADC		34

#define LPC32XX_CLK_HCLK_PLL	35



/* LPC32XX USB clocks */

#define LPC32XX_USB_CLK_I2C	1