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Commit 7d6cc0cd authored by Ramesh Shanmugasundaram's avatar Ramesh Shanmugasundaram Committed by Geert Uytterhoeven
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clk: renesas: r8a7795: Add DRIF clock 



This patch adds DRIF module clocks for r8a7795 SoC.

Signed-off-by: default avatarRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f7bb887f

drivers/clk/renesas/r8a7795-cpg-mssr.c

+8 −0
Original line number Diff line number Diff line
@@ -138,6 +138,14 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S3D4),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S3D4),

	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),

	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),

	DEF_MOD("drif4",		 511,	R8A7795_CLK_S3D2),

	DEF_MOD("drif3",		 512,	R8A7795_CLK_S3D2),

	DEF_MOD("drif2",		 513,	R8A7795_CLK_S3D2),

	DEF_MOD("drif1",		 514,	R8A7795_CLK_S3D2),

	DEF_MOD("drif0",		 515,	R8A7795_CLK_S3D2),

	DEF_MOD("hscif4",		 516,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif3",		 517,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),